MC9RS08KA8RM Datasheet, PDF (77/190 Pages) Freescale Semiconductor, Inc – MC9RS08KA8 Features

Chapter 8 Central Processor Unit (RS08CPUV1)
8.5 Summary Instruction Table
Instruction Set Summary Nomenclature
The nomenclature listed here is used in the instruction descriptions in Table 8-1 through Table 8-2.
Operators
( ) = Contents of register or memory location shown inside parentheses
← = Is loaded with (read: “gets”)
⇔ = Exchange with
& = Boolean AND
| = Boolean OR
⊕ = Boolean exclusive-OR
: = Concatenate
+ = Add
CPU registers
A=
CCR =
PC =
PCH =
PCL =
SPC =
SPCH =
SPCL =
Accumulator
Condition code register
Program counter
Program counter, higher order (most significant) six bits
Program counter, lower order (least significant) eight bits
Shadow program counter
Shadow program counter, higher order (most significant) six bits
Shadow program counter, lower order (least significant) eight bits
Memory and addressing
M = A memory location or absolute data, depending on addressing mode
rel =
X=
,X or D[X] =
The relative offset, which is the two’s complement number stored in the last
byte of machine code corresponding to a branch instruction
Pseudo index register, memory location $000F
Memory location $000E pointing to the memory location defined by the
pseudo index register (location $000F)
Condition code register (CCR) bits
Z = Zero indicator
C = Carry/borrow
CCR activity notation
– = Bit not affected
0 = Bit forced to 0
1 = Bit forced to 1
Þ = Bit set or cleared according to results of operation
U = Undefined after the operation
Machine coding notation
MC9RS08KA8 Series Reference Manual, Rev. 3
Freescale Semiconductor
77