MC9RS08KA8RM Datasheet, PDF (37/190 Pages) Freescale Semiconductor, Inc – MC9RS08KA8 Features

Chapter 4 Memory
The separate background debug controller can still be used for registers and RAM access. Via BDM
commands, flash mass erase is possible by writing to the flash control register that follows the flash mass
erase procedure listed in Section 4.6.3, “Flash Mass Erase Operation.”
Security can always be disengaged through the background debug interface when you:
1. Mass erase flash via background BDM commands or RAM loaded program.
2. Perform reset. The device boots up with security disengaged.
NOTE
When the device boots up to normal operating mode, where MS pin is high
during reset, with SECD programmed (SECD = 0), flash security is
engaged. BKGDPE is reset to 0, all BDM communication is blocked, and
background debug is not allowed.
4.7 Flash Registers and Control Bits
The flash module has a nonvolatile register NVOPT ($3FFC) in flash memory which is copied into the
corresponding control register FOPT ($0210) at reset.
4.7.1 Flash Options Register (FOPT and NVOPT)
During reset, the nonvolatile location NVOPT contents are copied from flash into FOPT. Bits 7 through 1
are not used and always read 0. This register may be read at any time, but writes have no meaning or effect.
To change the value in this register, erase and reprogram the NVOPT location in flash memory then issue
a new MCU reset.
7
6
5
4
3
2
1
R
0
0
0
0
0
0
0
W
Reset
This register is loaded from nonvolatile location NVOPT during reset.
= Unimplemented or Reserved
Figure 4-3. Flash Options Register (FOPT)
0
SECD
Table 4-2. FOPT Field Descriptions
Field
0
SECD
Description
Security State Code — This bit field determines the MCU security state. When the MCU is secured, the flash
memory contents cannot be accessed by instructions from any unsecured source including the background
debug interface; see Section 4.6.4, “Security.”
0 Security engaged.
1 Security disengaged.
MC9RS08KA8 Series Reference Manual, Rev. 3
Freescale Semiconductor
37