MC9RS08KA8RM Datasheet, PDF (66/190 Pages) Freescale Semiconductor, Inc – MC9RS08KA8 Features

Chapter 7 Keyboard Interrupt (RS08KBIV1)
Table 7-4. KBIPE Register Field Descriptions
Field
Description
7:0
KBIPEn
Keyboard Pin Enables — Each of the KBIPEn bits enables the corresponding keyboard interrupt pin.
0 Corresponding pin not enabled as keyboard interrupt.
1 Corresponding pin enabled as keyboard interrupt.
7.3.3 KBI Edge Select Register (KBIES)
KBIES contains the edge select control bits.
7
R
KBEDG7
W
Reset:
0
6
5
4
3
2
KBEDG6 KBEDG5 KBEDG4 KBEDG3 KBEDG2
0
0
0
0
0
Figure 7-4. KBI Edge Select Register (KBIES)
1
KBEDG1
0
0
KBEDG0
0
Table 7-5. KBIES Register Field Descriptions
Field
Description
7:0
KBEDGn
Keyboard Edge Selects — Each KBEDGn bit selects the falling edge/low level or rising edge/high level function
of the corresponding pin.
0 Falling edge/low level.
1 Rising edge/high level.
7.4 Functional Description
This on-chip peripheral module is called a keyboard interrupt (KBI) module because it was originally
designed to simplify the connection and use of row-column matrices of keyboard switches. However, these
inputs are also useful as extra external interrupt inputs and as an external means of waking the MCU from
stop or wait low-power modes.
The KBI module allows its pins to act as additional interrupt sources. Writing to the KBIPEn bits in the
keyboard interrupt pin enable register (KBIPE) independently enables or disables each KBI pin. Each KBI
pin can be configured as edge-sensitive or edge-and-level sensitive based on the KBMOD bit in the
keyboard interrupt status and control register (KBISC). Edge-sensitive can be software programmed to be
falling or rising; the level can be low or high. The polarity of the edge- or edge-and-level sensitivity is
selected using the KBEDGn bits in the keyboard interrupt edge select register (KBIES).
7.4.1 Edge Only Sensitivity
Synchronous logic is used to detect edges. A falling edge is detected when an enabled keyboard interrupt
(KBIPEn=1) input signal is seen as a logic 1 (the deasserted level) during one bus cycle and then a logic 0
(the asserted level) during the next cycle. A rising edge is detected when the input signal is seen as a logic
0 (the deasserted level) during one bus cycle and then a logic 1 (the asserted level) during the next
cycle.Before the first edge is detected, all enabled keyboard interrupt input signals must be at the
MC9RS08KA8 Series Reference Manual, Rev. 3
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Freescale Semiconductor