MC9RS08KA8RM Datasheet, PDF (52/190 Pages) Freescale Semiconductor, Inc – MC9RS08KA8 Features

Chapter 6 Parallel Input/Output Control
When a shared analog function is enabled for a pin, the input and output buffers are disabled. A value of
0 is read for any port data bit where the bit is an input (PTADDn = 0) and the input buffer is disabled. In
general, whenever a pin is shared with an alternative digital function and an analog function, the analog
function has priority such that if the digital and analog functions are enabled, the analog function controls
the pin.
It is useful to write to the port data register before changing the direction of a port pin to become an output.
This ensures the pin is not driven temporarily with an old data value that happened to be in the port data
register.
A set of registers associated with the parallel I/O ports is located in the high page register space that operate
independently of the parallel I/O registers. These registers are used to control pullup/pulldown and slew
rate for the pins. See Section 6.3, “Pin Control Registers.”
6.1 Pin Behavior in Low-Power Modes
In wait and stop modes, all pin states are maintained because internal logic stays powered up. Upon
recovery, all pin functions revert to the state they were in prior to entering stop mode.
6.2 Parallel I/O Registers
This section provides information about registers associated with the parallel I/O ports. The parallel I/O
data registers are located within the $001F memory boundary of the memory map, so that short and direct
addressing mode instructions can be used.
Refer to the tables in Chapter 4, “Memory,” for the absolute address assignments for all parallel I/O. This
section refers to registers and control bits only by their names. A Freescale Semiconductor-provided
equate or header file is normally used to translate these names into the appropriate absolute addresses.
6.2.1 Port A Registers
Port A parallel I/O function is controlled by the data and data direction registers described in this section.
7
R
0
W
Reset:
0
6
5
4
3
2
1
0
0
PTAD5
PTAD4
PTAD3
PTAD2
PTAD1
PTAD0
0
0
0
0
0
0
0
Figure 6-2. Port A Data Register (PTAD)
MC9RS08KA8 Series Reference Manual, Rev. 3
52
Freescale Semiconductor