MC9RS08KA8RM Datasheet, PDF (122/190 Pages) Freescale Semiconductor, Inc – MC9RS08KA8 Features

Internal Clock Source (S08ICSV1)
11.1.2.5 FLL Bypassed External (FBE)
In FLL bypassed external mode, the FLL is enabled and controlled by an external reference clock, but is
bypassed. The ICS supplies a clock derived from the external reference clock. The external reference clock
can be an external crystal/resonator supplied by an OSC controlled by the ICS, or it can be another external
clock source.
11.1.2.6 FLL Bypassed External Low Power (FBELP)
In FLL bypassed external low power mode, the FLL is disabled and bypassed, and the ICS supplies a clock
derived from the external reference clock. The external reference clock can be an external crystal/resonator
supplied by an OSC controlled by the ICS, or it can be another external clock source.
11.1.2.7 Stop (STOP)
In stop mode, the FLL is disabled and the internal or external reference clocks can be selected to be enabled
or disabled. The ICS does not provide an MCU clock source.
11.1.3 Block Diagram
Figure 11-2 is the ICS block diagram.
RANGE
HGO
Optional
External Reference
Clock Source
Block
EREFS
EREFSTEN
IREFSTEN
ERCLKEN
IRCLKEN
CLKS
BDIV
ICSERCLK
ICSIRCLK
Internal
Reference
LP
Clock
/ 2ⁿ
n=0-3
ICSOUT
IREFS
9
TRIM
DCO
/ 2ⁿ
n=0-7
RDIV_CLK
9
Filter
FLL
RDIV
Internal Clock Source Block
Figure 11-2. Internal Clock Source (ICS) Block Diagram
ICSFFCLK
MC9RS08KA8 Series Reference Manual, Rev. 3
122
Freescale Semiconductor