MC9RS08KA8RM Datasheet, PDF (181/190 Pages) Freescale Semiconductor, Inc – MC9RS08KA8 Features

BDC CLOCK
(TARGET MCU)
HOST DRIVE
TO BKGD PIN
Chapter 15 Development Support
HIGH IMPEDANCE
TARGET MCU
SPEEDUP PULSE
PERCEIVED START
OF BIT TIME
BKGD PIN
HIGH IMPEDANCE
R-C RISE
HIGH IMPEDANCE
10 CYCLES
10 CYCLES
EARLIEST START
OF NEXT BIT
HOST SAMPLES BKGD PIN
Figure 15-4. BDC Target-to-Host Serial Bit Timing (Logic 1)
Figure 15-5 shows the host receiving a logic 0 from the target MCU. Because the host is asynchronous to
the target, there is a 0-to-1 cycle delay from the host-generated falling edge on BKGD to the start of the
bit time as perceived by the target. The host initiates the bit time but the target finishes it. Because the target
wants the host to receive a logic 0, it drives the BKGD pin low for 13 BDC clock cycles, then briefly drives
it high to speed up the rising edge. The host samples the bit level approximately 10 cycles after starting
the bit time.
MC9RS08KA8 Series Reference Manual, Rev. 3
Freescale Semiconductor
181