MC9RS08KA8RM Datasheet, PDF (129/190 Pages) Freescale Semiconductor, Inc – MC9RS08KA8 Features

Internal Clock Source (S08ICSV1)
11.4.1.6 FLL Bypassed External Low Power (FBELP)
The FLL bypassed external low power (FBELP) mode is entered when all the following conditions occur:
• CLKS bits are written to 10.
• IREFS bit is written to 0.
• LP bit is written to 1.
In FLL bypassed external low power mode, the ICSOUT clock is derived from the external reference clock
and the FLL is disabled. The external reference clock is enabled.
11.4.1.7 Stop
Stop mode is entered whenever the MCU enters a STOP state. In this mode, all ICS clock signals are static
except in the following cases:
ICSIRCLK will be active in stop mode when both of the following conditions occur:
• IRCLKEN bit is written to 1
• IREFSTEN bit is written to 1
ICSERCLK will be active in stop mode when both of the following conditions occur:
• ERCLKEN bit is written to 1
• EREFSTEN bit is written to 1
11.4.2 Mode Switching
When switching between FLL engaged internal (FEI) and FLL engaged external (FEE) modes, the IREFS
bit can be changed at anytime, but the RDIV bits must be changed simultaneously so that the resulting
frequency stays in the range of 31.25 kHz to 39.0625 kHz. After a change in the IREFS value, the FLL
will begin locking again after a few full cycles of the resulting divided reference frequency.
The CLKS bits can also be changed at anytime, but the RDIV bits must be changed simultaneously so that
the resulting frequency stays in the range of 31.25 kHz to 39.0625 kHz. The actual switch to the newly
selected clock will not occur until after a few full cycles of the new clock. If the newly selected clock is
not available, the previous clock will remain selected.
11.4.3 Bus Frequency Divider
The BDIV bits can be changed at anytime and the actual switch to the new frequency will occur
immediately.
11.4.4 Low Power Bit Usage
The low power bit (LP) is provided to allow the FLL to be disabled and thus conserve power when it is
not being used. However, in some applications it may be desirable to enable the FLL and allow it to lock
for maximum accuracy before switching to an FLL engaged mode. Do this by writing the LP bit to 0.
MC9RS08KA8 Series Reference Manual, Rev. 3
Freescale Semiconductor
129