MC9RS08KA8RM Datasheet, PDF (23/190 Pages) Freescale Semiconductor, Inc – MC9RS08KA8 Features

Chapter 2 Pins and Connections
bypass capacitor such as a 0.1μF ceramic capacitor, located as near to the MCU power pins as practical to
suppress high-frequency noise.
2.4.2 PTA5/TCLK/RESET/V_PP Pin
After a power-on reset (POR) into user mode, the PTA5/TCLK/RESET/V_pp pin defaults to a
general-purpose input port pin, PTA5. Setting RSTPE in SOPT configures the pin to be the RESET input
pin. After configured as RESET, the pin remains as RESET until the next reset. The RESET pin can
be used to reset the MCU from an external source when the pin is driven low. When enabled as the RESET
pin (RSTPE = 1), the internal pullup device is automatically enabled.
External V_PP voltage (typically 12 V, see MC9RS08KA8 Series Data Sheet) is required on this pin when
performing flash programming or erasing. The V_PP connection is always connected to the internal flash
module regardless of the pin function. To avoid over stressing the flash, external V_PP voltage must be
removed and voltage higher than V_DD must be avoided when flash programming or erasing does not occur.
NOTE
This pin does not contain a clamp diode to V_DD and must not be driven
above V_DD when flash programming or erasing does not occur.
2.4.3 PTA4/ACMPO/BKGD/MS Pin
The background/mode select function is shared with an output-only pin on PTA4 pin and the optional
analog comparator output. While in reset, the pin functions as a mode select pin. Immediately after reset
rises, the pin functions as the background pin and can be used for background debug communication.
While functioning as a background / mode select pin, this pin has an internal pullup device enabled. To use
as an output-only port, clear BKGDPE in SOPT.
If nothing is connected to this pin, the MCU enters normal operating mode at the rising edge of reset. If a
debug system is connected to the 6-pin standard background debug header, it can hold BKGD/MS low
during the power-on-reset, which forces the MCU to active background mode.
The BKGD pin is used primarily for background debug controller (BDC) communications using a custom
protocol that uses 16 clock cycles of the target MCU’s BDC clock per bit time. The target MCU’s BDC
clock equals the bus clock rate; therefore, significant capacitance must not be connected to the BKGD/MS
pin that could interfere with background serial communications.
Although the BKGD pin is a pseudo open-drain pin, the background debug communication protocol
provides brief, actively driven, high speedup pulses to ensure fast rise times. Small capacitances from the
internal pullup device do not affect rise and fall times on the BKGD pin.
2.4.4 General-Purpose I/O and Peripheral Ports
The remaining pins are shared among general-purpose I/O and on-chip peripheral functions such as timers
and the analog comparator. Immediately after reset, all of these pins are configured as high-impedance
general-purpose inputs with internal pullup/pulldown devices disabled.
MC9RS08KA8 Series Reference Manual, Rev. 3
Freescale Semiconductor
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