MC9RS08KA8RM Datasheet, PDF (55/190 Pages) Freescale Semiconductor, Inc – MC9RS08KA8 Features

Chapter 6 Parallel Input/Output Control
Table 6-6. PTCDD Register Field Descriptions
Field
3:0
PTCDD[3:0]
Description
Data Direction for Port C Bits — These read/write bits control the direction of port C pins and what is read
for PTCD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port C bit n and PTCD reads return the contents of PTCDn.
6.3 Pin Control Registers
This section provides information about the registers associated with the parallel I/O ports that are used
for pin control functions.
Refer to the tables in Chapter 4, “Memory,” for the absolute address assignments of the pin control
registers. This section refers to registers and control bits only by their names. A Freescale
Semiconductor-provided equate or header file normally is used to translate these names into the
appropriate absolute addresses.
NOTE
An output pin can be selected to have high output drive strength by setting
the corresponding bit in the drive strength select register (PTxDSn). When
high drive is selected, a pin is capable of sourcing and sinking greater
current. Even though every I/O pin can be selected as high drive, do not
exceed the total current source and sink limits for the MCU. Drive strength
selection affects the DC behavior of I/O pins. However, the AC behavior is
also affected. High drive allows a pin to drive a greater load with the same
switching speed as a low drive enabled pin into a smaller load. Because of
this, the EMC emissions may be affected by enabling pins as high drive.
6.3.1 Port A Pin Control Registers
The pins associated with port A are controlled by the registers provided in this section. These registers
control the pin pullup/pulldown and slew rate of the port A pins independent of the parallel I/O registers.
6.3.1.1 Internal Pulling Device Enable
An internal pulling device can be enabled for each port pin by setting the corresponding bit in the pulling
device enable register (PTAPEn). The pulling device is disabled if the pin is configured as an output by the
parallel I/O control logic or any shared peripheral output function regardless of the state of the
corresponding pulling-device-enable-register bit. The pulling device is also disabled if the analog function
controls the pin.
MC9RS08KA8 Series Reference Manual, Rev. 3
Freescale Semiconductor
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