MC9RS08KA8RM Datasheet, PDF (183/190 Pages) Freescale Semiconductor, Inc – MC9RS08KA8 Features

Chapter 15 Development Support
• Subsequent bits must occur within 512 BDC cycles of the last bit sent.
15.4 BDC Registers and Control Bits
The BDC contains two non-CPU accessible registers:
• The BDC status and control register (BDCSCR) is an 8-bit register containing control and status
bits for the background debug controller.
• The BDC breakpoint register (BDCBKPT) holds a 16-bit breakpoint match address.
These registers are accessed with dedicated serial BDC commands and are not located in the memory
space of the target MCU (so they do not have addresses and cannot be accessed by user programs).
Some of the bits in the BDCSCR have write limitations; otherwise, these registers may be read or written
at any time. For example, the ENBDM control bit may not be written while the MCU is in active
background mode. This prevents the ambiguous condition of the control bit forbidding active background
mode while the MCU is already in active background mode. Also, the status bits (BDMACT, WS, and
WSF) are read-only status indicators and can never be written by the WRITE_CONTROL serial BDC
command.
15.4.1 BDC Status and Control Register (BDCSCR)
This register can be read or written by serial BDC commands (READ_STATUS and WRITE_CONTROL)
but is not accessible to user programs because it is not located in the normal memory map of the MCU.
7
6
5
4
3
2
1
0
R
BDMACT
0
WS
WSF
0
ENBDM
BKPTEN
FTS
W
Normal
Reset
0
0
0
0
0
0
0
0
Reset in
Active BDM:
1
1
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 15-6. BDC Status and Control Register (BDCSCR)
Table 15-1. BDCSCR Register Field Descriptions
Field
Description
7
ENBDM
6
BDMACT
Enable BDM (Permit Active Background Mode) — Typically, this bit is written to 1 by the debug host shortly
after the beginning of a debug session or whenever the debug host resets the target and remains 1 until a normal
reset clears it. If the application can go into stop mode, this bit is required to be set if debugging capabilities are
required.
0 BDM cannot be made active (non-intrusive commands still allowed).
1 BDM can be made active to allow active background mode commands.
Background Mode Active Status — This is a read-only status bit.
0 BDM not active (user application program running).
1 BDM active and waiting for serial commands.
MC9RS08KA8 Series Reference Manual, Rev. 3
Freescale Semiconductor
183