MC9RS08KA8RM Datasheet, PDF (79/190 Pages) Freescale Semiconductor, Inc – MC9RS08KA8 Features

Chapter 8 Central Processor Unit (RS08CPUV1)
Source
Form
ADC #opr8i
ADC opr8a
ADC ,X ⁽¹⁾
ADC X
ADD #opr8i
ADD opr8a
ADD opr4a
ADD ,X ⁽¹⁾
ADD X
AND #opr8i
AND opr8a
AND ,X ⁽¹⁾
AND X
Table 8-1. Instruction Set Summary (Sheet 1 of 6)
Description
Add with Carry
Add without Carry
Logical AND
Operation
A ← (A) + (M) + (C)
A ← (A) + (X) + (C)
A ← (A) + (M)
A ← (A) & (M)
A ← (A) & (X)
Effect
on
CCR
ZC
IMM
¦
¦
DIR
IX
DIR
IMM
DIR
¦ ¦ TNY
IX
DIR
IMM
¦
DIR
— _IX
DIR
A9
ii
2
B9
dd
3
3
B9
0E
3
B9
0F
AB
2
BB
6x
6E
ii
dd
3
3
3
3
6F
A4
ii
2
B4
dd
3
3
B4
0E
3
B4
0F
ASLA⁽¹⁾
BCC rel
BCLR n,opr8a
BCLR n,D[X]
BCLR n,X
BCS rel
BEQ rel
BGND
Arithmetic Shift Left
C
b7
0
¦ ¦ INH
48
b0
Branch if Carry Bit Clear
PC ← (PC) + $0002 + rel, if (C) = 0
— — REL
34
DIR (b0) 11
DIR (b1) 13
DIR (b2) 15
DIR (b3) 17
DIR (b4) 19
DIR (b5) 1B
Clear Bit n in Memory
Mn ← 0
DIR (b6) 1D
DIR (b7) 1F
IX (b0)
11
IX (b1)
13
IX (b2)
15
—
—
IX (b3)
IX (b4)
17
19
IX (b5)
1B
IX (b6)
1D
IX (b7)
1F
DIR (b0) 11
DIR (b1) 13
DIR (b2) 15
DIR (b3) 17
DIR (b4) 19
DIR (b5) 1B
DIR (b6) 1D
DIR (b7) 1F
Branch if Carry Bit Set
(Same as BLO)
PC ← (PC) + $0002 + rel, if (C) = 1 — — REL
35
Branch if Equal
PC ← (PC) + $0002 + rel, if (Z) = 1 — — REL
37
Background
Enter Background Debug Mode
— — INH
BF
1
rr
3
dd
5
dd
5
5
dd
5
dd
5
dd
5
5
dd
5
dd
5
dd
5
5
0E
5
0E
5
5
0E
5
0E
5
0E
5
5
0E
5
0E
0E
5
5
5
0F
5
0F
5
0F
0F
0F
0F
0F
0F
rr
3
rr
3
5+
1. This is a pseudo instruction supported by the normal RS08 instruction set.
2. This instruction is different from that of the HC08 and HCS08 in that the RS08 does not auto-increment the index register.
MC9RS08KA8 Series Reference Manual, Rev. 3
Freescale Semiconductor
79