MC9RS08KA8RM Datasheet, PDF (54/190 Pages) Freescale Semiconductor, Inc – MC9RS08KA8 Features

Chapter 6 Parallel Input/Output Control
R
W
Reset:
7
PTBDD7
0
6
PTBDD6
5
PTBDD5
4
PTBDD4
3
PTBDD3
2
PTBDD2
0
0
0
0
0
Figure 6-5. Port B Data Direction Register (PTBDD)
1
PTBDD1
0
0
PTBDD0
0
Table 6-4. PTBDD Register Field Descriptions
Field
7:0
PTBDD[7:0]
Description
Data Direction for Port B Bits — These read/write bits control the port B pins direction and what is read for
PTBD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port B bit n and PTBD reads return the contents of PTBDn.
6.2.3 Port C Registers
Port C parallel I/O function is controlled by the data and data direction registers described in this section.
7
R
0
W
Reset:
0
6
5
4
3
2
1
0
0
0
0
PTCD3
PTCD2
PTCD1
PTCD0
0
0
0
0
0
0
0
Figure 6-6. Port C Data Register (PTCD)
Table 6-5. PTCD Register Field Descriptions
Field
Description
3:0
PTCD[3:0]
Port C Data Register Bits — For port C pins that are inputs, reads return the logic level on the pin. For port C
pins configured as outputs, reads return the last value written to this register. Writes are latched into all bits of
this register. For port C pins configured as outputs, the logic level is driven out on the corresponding MCU pin.
Reset forces PTCD to all 0s, but these 0s are not driven out on the corresponding pins because reset also
configures all port pins as high-impedance inputs with pullup/pulldowns disabled.
7
R
0
W
Reset:
0
6
5
4
3
2
0
0
0
PTCDD3 PTCDD2
0
0
0
0
0
Figure 6-7. Port C Data Direction Register (PTCDD)
1
PTCDD1
0
0
PTCDD0
0
MC9RS08KA8 Series Reference Manual, Rev. 3
54
Freescale Semiconductor