MC9RS08KA8RM Datasheet, PDF (130/190 Pages) Freescale Semiconductor, Inc – MC9RS08KA8 Features

Internal Clock Source (S08ICSV1)
11.4.5 Internal Reference Clock
When IRCLKEN is set, the internal reference clock signal will be presented as ICSIRCLK, which can be
used as an additional clock source. The ICSIRCLK frequency can be re-targeted by trimming the period
of the internal reference clock. This can be done by writing a new value to the TRIM bits in the ICSTRM
register. Writing a larger value will slow down the ICSIRCLK frequency, and writing a smaller value to
the ICSTRM register will speed up the ICSIRCLK frequency. The TRIM bits will effect the ICSOUT
frequency if the ICS is in FLL engaged internal (FEI), FLL bypassed internal (FBI), or FLL bypassed
internal low power (FBILP) mode. The TRIM and FTRIM value will not be affected by a reset.
Until ICSIRCLK is trimmed, programming low reference divider (RDIV) factors may result in ICSOUT
frequencies exceeding the maximum chip-level frequency and violating the chip-level clock timing
specifications (see the Device Overview chapter).
If IREFSTEN is set and the IRCLKEN bit is written to 1, the ICSIRCLK will keep running during stop
mode in order to provide a fast recovery upon exiting stop.
All MCU devices are factory programmed with a trim value in a reserved memory location. This value can
be copied to the ICSTRM register during reset initialization. The factory trim value does not include the
FTRIM bit. For finer precision, the user can trim the internal oscillator in the application and set the
FTRIM bit accordingly.
11.4.6 Optional External Reference Clock
The ICS module can support an external reference clock with frequencies between 31.25 kHz to 5 MHz
in all modes. When the ERCLKEN is set, the external reference clock signal will be presented as
ICSERCLK, which can be used as an additional clock source. When IREFS = 1, the external reference
clock will not be used by the FLL and will only be used as ICSERCLK. In these modes, the frequency can
be equal to the maximum frequency the chip-level timing specifications support (see the Device Overview
chapter).
If EREFSTEN is set and the ERCLKEN bit is written to 1, the ICSERCLK will keep running during stop
mode in order to provide a fast recovery upon exiting stop.
11.4.7 Fixed Frequency Clock
The ICS presents the divided FLL reference clock as ICSFFCLK for use as an additional clock source for
peripheral modules. The ICS provides an output signal (ICSFFE) which indicates when the ICS is
providing ICSOUT frequencies four times or greater than the divided FLL reference clock (ICSFFCLK).
In FLL engaged mode (FEI and FEE) this is always true and ICSFFE is always high. In ICS bypass mode,
ICSFFE will get asserted for the following combinations of BDIV and RDIV values:
• BDIV = 00 (divide by 1), RDIV ≥ 010
• BDIV = 01 (divide by 2), RDIV ≥ 011
• BDIV = 10 (divide by 4), RDIV ≥ 100
• BDIV = 11 (divide by 8), RDIV ≥ 101
MC9RS08KA8 Series Reference Manual, Rev. 3
130
Freescale Semiconductor