MC9RS08KA8RM Datasheet, PDF (103/190 Pages) Freescale Semiconductor, Inc – MC9RS08KA8 Features

Analog-to-Digital Converter (RS08ADC10V1)
Table 10-5. ADCCFG Register Field Descriptions (continued)
Field
Description
4
ADLSMP
3:2
MODE
1:0
ADICLK
Long Sample Time Configuration — ADLSMP selects between long and short sample periods. This adjusts
the sample period to allow higher impedance inputs to be accurately sampled or to maximize conversion speed
for lower impedance inputs. Longer sample times can also be used to lower overall power consumption when
continuous conversions are enabled if high conversion rates are not required.
0 Short sample time
1 Long sample time
Conversion Mode Selection — MODE bits are used to select between 10- or 8-bit operation. See Table 10-7.
Input Clock Select — ADICLK bits select the input clock source to generate the internal clock ADCK. See
Table 10-8.
ADIV
00
01
10
11
MODE
00
01
10
11
ADICLK
00
01
10
11
Table 10-6. Clock Divide Select
Divide Ratio
1
2
4
8
Clock Rate
Input clock
Input clock ÷ 2
Input clock ÷ 4
Input clock ÷ 8
Table 10-7. Conversion Modes
Mode Description
8-bit conversion (N=8)
Reserved
10-bit conversion (N=10)
Reserved
Table 10-8. Input Clock Select
Selected Clock Source
Bus clock
Bus clock divided by 2
Alternate clock (ALTCLK)
Asynchronous clock (ADACK)
MC9RS08KA8 Series Reference Manual, Rev. 3
Freescale Semiconductor
103