MC9RS08KA8RM Datasheet, PDF (116/190 Pages) Freescale Semiconductor, Inc – MC9RS08KA8 Features

Analog-to-Digital Converter (RS08ADC10V1)
• V_SSAD (and V_REFL, if connected) is connected to V_SS at a quiet point in the ground plane.
• Operate the MCU in wait or stop mode before initiating (hardware triggered conversions) or
immediately after initiating (hardware or software triggered conversions) the ADC conversion.
— For software triggered conversions, immediately follow the write to the ADCSC1 with a WAIT
instruction or STOP instruction.
— For stop mode operation, select ADACK as the clock source. Operation in stop reduces V_DD
noise but increases effective conversion time due to stop recovery.
• There is no I/O switching, input or output, on the MCU during the conversion.
In some situations where external system activity causes radiated or conducted noise emissions or
excessive V_DD noise is coupled into the ADC. In these situations, or when the MCU cannot be placed in
wait or stop or I/O activity can not be halted, try the following recommended actions to reduce the effect
of noise on the accuracy:
• Place a 0.01 μF capacitor (C_AS) on the selected input channel to V_REFL or V_SSAD (this improves
noise issues, but can affect sample rate based upon the external analog source resistance).
• Average the result by converting the analog input many times in succession and dividing the sum
of the results. Four samples are required to eliminate the effect of a 1LSB, one-time error.
• Reduce the effect of synchronous noise by operating off the asynchronous clock (ADACK) and
averaging. Noise that is synchronous to ADCK cannot be averaged out.
10.6.2.4 Code Width and Quantization Error
The ADC quantizes the ideal straight-line transfer function into 1024 steps (in 10-bit mode). Each step
ideally has the same height (1 code) and width. The width is defined as the delta between the transition
points to one code and the next. The ideal code width for an N bit converter (in this case N can be 8 or 10),
defined as 1LSB, is:
1LSB = (V_REFH – V_REFL) / 2^N
Eqn. 10-1
There is an inherent quantization error due to the digitization of the result. For 8-bit or 10-bit conversions,
the code transitions when the voltage is at the midpoint between the points where the straight line transfer
function is exactly represented by the actual transfer function. Therefore, the quantization error will be ±
1/2LSB in 8- or 10-bit mode. As a consequence, the code width of the first ($000) conversion is only 1/2LSB
and the code width of the last ($FF or $3FF) is 1.5LSB.
10.6.2.5 Linearity Errors
The ADC might also exhibit non-linearity of several forms. Every effort has been made to reduce these
errors but the application must be aware of them because they affect overall accuracy. These errors are:
• Zero-scale error (E_ZS) (sometimes called offset) — The difference between the actual code width
of the first conversion and the ideal code width (1/2LSB). Note, if the first conversion is $001, then
the difference between the actual $001 code width and its ideal (1LSB) is used.
• Full-scale error (E_FS) — The difference between the actual code width of the last conversion and
the ideal code width (1.5LSB). Note, if the last conversion is $3FE, then the difference between the
actual $3FE code width and its ideal (1LSB) is used.
MC9RS08KA8 Series Reference Manual, Rev. 3
116
Freescale Semiconductor