MC9RS08KA8RM Datasheet, PDF (61/190 Pages) Freescale Semiconductor, Inc – MC9RS08KA8 Features

Chapter 6 Parallel Input/Output Control
7
R
0
W
Reset:
0
6
5
4
3
2
1
0
0
0
PTCSE3
PTCSE2
PTCSE1
0
0
0
1
1
1
Figure 6-18. Slew Rate Enable for Port C Register (PTCSE)
0
PTCSE0
1
Table 6-17. PTCSE Register Field Descriptions
Field
Description
3:0
PTCSE[3:0]
Output Slew Rate Enable for Port C Bits — Each of these control bits determines whether the output slew
rate control is enabled for the associated PTC pin. For port C pins that are configured as inputs, these bits have
no effect.
0 Output slew rate control disabled for port C bit n.
1 Output slew rate control enabled for port C bit n.
6.3.3.4 Port C Drive Strength Selection Register (PTCDS)
7
R
0
W
Reset
0
6
5
4
3
2
1
0
0
0
PTCDS3
PTCDS2
PTCDS1
0
0
0
0
0
0
Figure 6-19. Output Drive Strength Selection for Port C (PTCDS)
0
PTCDS0
0
Table 6-18. PTCDS Register Field Descriptions
Field
Description
3:0
Output Drive Strength Selection for Port C Bits — Each of these control bits is selected between low and high
PTCDS[3:0] output drive for the associated PTC pin.
0 Low output drive enabled for port C bit n.
1 High output drive enabled for port C bit n.
MC9RS08KA8 Series Reference Manual, Rev. 3
Freescale Semiconductor
61