MC9RS08KA8RM Datasheet, PDF (82/190 Pages) Freescale Semiconductor, Inc – MC9RS08KA8 Features

Chapter 8 Central Processor Unit (RS08CPUV1)
Table 8-1. Instruction Set Summary (Sheet 4 of 6)
Source
Form
BSR rel
CBEQA #opr8i,rel
CBEQ opr8a,rel
CBEQ ,X,rel ^(1),(2)
CBEQ X,rel ⁽¹⁾
CLC
CLR opr8a
CLR opr5a
CLR ,X ⁽¹⁾
CLRA
CLRX ⁽¹⁾
CMP #opr8i
CMP opr8a
CMP ,X ⁽¹⁾
CMP X ⁽¹⁾
COMA
DBNZ opr8a,rel
DBNZ ,X,rel ⁽¹⁾
DBNZA rel
DBNZX rel ⁽¹⁾
DEC opr8a
DEC opr4a
DEC ,X ⁽¹⁾
DECA
DEC X
EOR #opr8i
EOR opr8a
EOR ,X ⁽¹⁾
EOR X
INC opr8a
INC opr4a
INC ,X ⁽¹⁾
INCA
INCX ⁽¹⁾
JMP opr16a
JSR opr16a
LDA #opr8i
LDA opr8a
LDA opr5a
LDA ,X ⁽¹⁾
Description
Operation
Effect
on
CCR
ZC
Branch Subroutine
PC ← (PC) + 2
Push PC to shadow PC
PC ← (PC) + rel
— — REL
Compare and Branch if
Equal
PC ← (PC) + $0003 + rel, if (A) – (M) = $00
PC ← (PC) + $0003 + rel, if (A) – (M) = $00
PC ← (PC) + $0003 + rel, if (A) – (X) = $00
IMM
—
—
DIR
IX
DIR
Clear Carry Bit
C←0
— 0 INH
Clear
M ← $00
A ← $00
X ← $00
DIR
SRT
1 — IX
INH
INH
Compare Accumulator
with Memory
(A) – (M)
(A) – (X)
IMM
¦
¦
DIR
IX
INH
Complement
(One’s Complement)
A ← (A)
¦ 1 INH
A ← (A) – $01 or M ← (M) - $01
PC ← (PC) + $0003 + rel if (result) ≠ 0 for DBNZ
DIR
Decrement and Branch if
Not Zero
direct
PC ← (PC) + $0002 + rel if (result) ≠ 0 for
DBNZA
—
—
IX
INH
X ← (X) – $01
INH
PC ← (PC) + $0003 + rel if (result) ≠ 0
Decrement
M ← (M) – $01
A ← (A) – $01
X ← (X) – $01
DIR
TNY
¦ — IX
INH
DIR
Exclusive OR
Memory with
Accumulator
A ← (A ⊕ M)
A ← (A ⊕ X)
IMM
¦
—
DIR
IX
DIR
Increment
M ← (M) + $01
A ← (A) + $01
X ← (X) + $01
DIR
TNY
¦ — IX
INH
INH
Jump
PC ← Effective Address
— — EXT
Jump to Subroutine
PC ← (PC) + 3
Push PC to shadow PC
PC ← Effective Address
— — EXT
Load Accumulator from
Memory
A ← (M)
IMM
¦
—
DIR
SRT
IX
AD rr
3
41
ii rr 4
31
dd rr 5
31
0E rr 5
31
0F rr 5
38
1
3F
dd 3
8x / 9x
2
8E
2
4F
1
8F
2
A1
ii
2
B1
dd
3
B1
0E 3
B1
0F 3
43
1
3B
dd rr 7
3B
0E rr 7
4B
rr
4
3B
0F rr 7
3A
dd
5
5x
4
5E
4
4A
1
5F
4
A8
ii
2
B8
dd
3
B8
0E 3
B8
0F 3
3C
dd
5
2x
4
2E
4
4C
1
2F
4
BC hh ll 4
BD hh ll 4
A6
ii
2
B6
dd
3
Cx/Dx
3
CE
3
1. This is a pseudo instruction supported by the normal RS08 instruction set.
2. This instruction is different from that of the HC08 and HCS08 in that the RS08 does not auto-increment the index register.
MC9RS08KA8 Series Reference Manual, Rev. 3
82
Freescale Semiconductor