MC9RS08KA8RM Datasheet, PDF (128/190 Pages) Freescale Semiconductor, Inc – MC9RS08KA8 Features

Internal Clock Source (S08ICSV1)
11.4.1.2 FLL Engaged External (FEE)
The FLL engaged external (FEE) mode is entered when all the following conditions occur:
• CLKS bits are written to 00
• IREFS bit is written to 0
• RDIV bits are written to divide reference clock to be within the range of 31.25 kHz to 39.0625 kHz
In FLL engaged external mode, the ICSOUT clock is derived from the FLL clock which is controlled by
the external reference clock. The FLL loop will lock the frequency to 512 times the filter frequency, as
selected by the RDIV bits. The external reference clock is enabled.
11.4.1.3 FLL Bypassed Internal (FBI)
The FLL bypassed internal (FBI) mode is entered when all the following conditions occur:
• CLKS bits are written to 01
• IREFS bit is written to 1.
• LP bit is written to 0
In FLL bypassed internal mode, the ICSOUT clock is derived from the internal reference clock. The FLL
clock is controlled by the internal reference clock, and the FLL loop will lock the FLL frequency to 512
times the filter frequency, as selected by the RDIV bits. The internal reference clock is enabled.
11.4.1.4 FLL Bypassed Internal Low Power (FBILP)
The FLL bypassed internal low power (FBILP) mode is entered when all the following conditions occur:
• CLKS bits are written to 01
• IREFS bit is written to 1.
• LP bit is written to 1
In FLL bypassed internal low power mode, the ICSOUT clock is derived from the internal reference clock
and the FLL is disabled. The internal reference clock is enabled.
11.4.1.5 FLL Bypassed External (FBE)
The FLL bypassed external (FBE) mode is entered when all the following conditions occur:
• CLKS bits are written to 10.
• IREFS bit is written to 0.
• LP bit is written to 0.
In FLL bypassed external mode, the ICSOUT clock is derived from the external reference clock. The FLL
clock is controlled by the external reference clock, and the FLL loop will lock the FLL frequency to 512
times the filter frequency, as selected by the RDIV bits. The external reference clock is enabled.
MC9RS08KA8 Series Reference Manual, Rev. 3
128
Freescale Semiconductor