MC9RS08KA8RM Datasheet, PDF (109/190 Pages) Freescale Semiconductor, Inc – MC9RS08KA8 Features

Analog-to-Digital Converter (RS08ADC10V1)
10.4.4.4 Power Control
The ADC module remains in idle until a conversion is initiated. If ADACK is selected as the conversion
clock source, the ADACK clock generator is also enabled.
Setting ADLPC can reduce power consumption. resulting in a lower maximum value for f_ADCK (see the
electrical specifications).
10.4.4.5 Total Conversion Time
The total conversion time depends on the sample time (as determined by ADLSMP), the MCU bus
frequency, the conversion mode (8-bit or 10-bit), and the frequency of the conversion clock (f_ADCK). After
the module becomes active, sampling of the input begins. ADLSMP is used to select between short and
long sample times.When sampling completes, the converter is isolated from the input channel and a
successive approximation algorithm is performed to determine the digital value of the analog signal. The
conversion result transfers to ADCRH and ADCRL upon completion of the conversion algorithm.
• If the bus frequency is less than the f_ADCK frequency, precise sample time for continuous
conversions cannot be guaranteed when short sample is enabled (ADLSMP=0).
• If the bus frequency is less than 1/11th of the f_ADCK frequency, precise sample time for continuous
conversions cannot be guaranteed when long sample is enabled (ADLSMP=1).
The maximum total conversion time for different conditions is summarized in Table 10-12.
Table 10-12. Total Conversion Time vs. Control Conditions
Conversion Type
Single or first continuous 8-bit
Single or first continuous 10-bit
Single or first continuous 8-bit
Single or first continuous 10-bit
Single or first continuous 8-bit
Single or first continuous 10-bit
Single or first continuous 8-bit
Single or first continuous 10-bit
Subsequent continuous 8-bit;
f_BUS > f_ADCK
Subsequent continuous 10-bit;
f_BUS > f_ADCK
Subsequent continuous 8-bit;
f_BUS > f_ADCK/11
Subsequent continuous 10-bit;
f_BUS > f_ADCK/11
ADICLK
0x, 10
0x, 10
0x, 10
0x, 10
11
11
11
11
xx
xx
xx
xx
ADLSMP
0
0
1
1
0
0
1
1
0
0
1
1
Max Total Conversion Time
20 ADCK cycles + 5 bus clock cycles
23 ADCK cycles + 5 bus clock cycles
40 ADCK cycles + 5 bus clock cycles
43 ADCK cycles + 5 bus clock cycles
5 μs + 20 ADCK + 5 bus clock cycles
5 μs + 23 ADCK + 5 bus clock cycles
5 μs + 40 ADCK + 5 bus clock cycles
5 μs + 43 ADCK + 5 bus clock cycles
17 ADCK cycles
20 ADCK cycles
37 ADCK cycles
40 ADCK cycles
The chosen clock source and the divide ratio determine the maximum total conversion time. The clock
source is selectable by the ADICLK bits, and the divide ratio is specified by the ADIV bits.
MC9RS08KA8 Series Reference Manual, Rev. 3
Freescale Semiconductor
109