MC9RS08KA8RM Datasheet, PDF (51/190 Pages) Freescale Semiconductor, Inc – MC9RS08KA8 Features

Chapter 6
Parallel Input/Output Control
This chapter explains software controls related to parallel input/output (I/O) and pin control. See
Chapter 2, “Pins and Connections,” for more information about pin assignments and external hardware
considerations for these pins.
All these I/O pins are shared with on-chip peripheral functions (see Table 2-1). The peripheral modules
have priority over the I/Os. When a peripheral is enabled, the I/O functions associated with the shared pins
are disabled. After reset, the shared peripheral functions are disabled so the I/O controls the pins. All the
I/Os are configured as inputs (PTADDn = 0) with pullup/pulldown devices disabled (PTAPEn = 0), except
for output-only pin PTA4, which defaults to the BKGD/MS function. All pins’ default-low-drive strengths
are selected (PTxDSn= 0) after reset
Reading and writing parallel I/Os is performed through the port data registers. The direction, either input
or output, is controlled through the port data direction registers. The block diagram in Figure 6-1 illustrates
the parallel I/O port function for an individual pin.
PTADDn
DQ
Output Enable
PTADn
DQ
Output Data
1
Port Read
Data
0
Synchronizer
Input Data
BUSCLK
Figure 6-1. Parallel I/O Block Diagram
The data direction control bit (PTADDn) determines whether the output buffer for the associated pin is
enabled, and also controls the source for port data register reads. The input buffer for the associated pin is
always enabled unless the pin is enabled as an analog function or is an output-only pin.
When a shared digital function is enabled for a pin, the shared function controls the output buffer.
However, the data direction register bit continues controlling the source for reads of the port data register.
MC9RS08KA8 Series Reference Manual, Rev. 3
Freescale Semiconductor
51