MC9RS08KA8RM Datasheet, PDF (57/190 Pages) Freescale Semiconductor, Inc – MC9RS08KA8 Features

Chapter 6 Parallel Input/Output Control
7
R
0
W
Reset:
0
6
5
4
3
2
1
0
0
PTASE4
PTASE3
PTASE2
PTASE1
0
0
1
1
1
1
Figure 6-10. Slew Rate Enable for Port A Register (PTASE)
0
PTASE0
1
Table 6-9. PTASE Register Field Descriptions
Field
4:0
PTASE[4:0]
Description
Output Slew Rate Enable for Port A Bits — Each of these control bits determines whether the output slew
rate control is enabled for the associated PTA pin. For port A pins configured as inputs, these bits have no
effect.
0 Output slew rate control disabled for port A bit n.
1 Output slew rate control enabled for port A bit n.
6.3.1.4 Port A Drive Strength Selection Register (PTADS)
7
6
5
4
3
2
1
0
R
0
0
0
PTADS4
PTADS3
PTADS2
PTADS1
PTADS0
W
Reset
0
0
0
0
0
0
0
0
Figure 6-11. Output Drive Strength Selection for Port A (PTASE)
Table 6-10. PTASE Register Field Descriptions
Field
Description
4:0
PTADS[4:0]
Output Drive Strength Selection for Port A Bits — Each of these control bits selects between low and high
output drive for the associated PTA pin.
0 Low output drive enabled for port A bit n.
1 High output drive enabled for port A bit n.
6.3.2 Port B Pin Control Registers
The pins associated with port B are controlled by the registers provided in this section. These registers
control the pin pullup/pulldown and slew rate of the port B pins independent of the parallel I/O registers.
6.3.2.1 Internal Pulling Device Enable
An internal pulling device can be enabled for each port pin by setting the corresponding bit in the pulling
device enable register (PTBPEn). The pulling device is disabled if the pin is configured as an output by the
parallel I/O control logic or any shared peripheral output function regardless of the state of the
corresponding pulling device enable register bit. The pulling device is also disabled if the analog function
controls the pin.
MC9RS08KA8 Series Reference Manual, Rev. 3
Freescale Semiconductor
57