DS580 Datasheet, PDF (9/42 Pages) Xilinx, Inc – Optional MDIO interface for PHY access

LogiCORE IP XPS Ethernet Lite Media Access Controller
The dual port memory is allocated so that 2K bytes are dedicated to the transmit function and 2K bytes are dedi-
cated to the receive function. This memory is capable of holding one maximum length ethernet packet in the receive
and transmit memory areas simultaneously.
Transmit Interface
The transmit data should be stored in the dual port memory starting at address C_BASEADDR + 0x0. Due to the
word aligned addressing, the second 4 bytes are located at C_BASEADDR + 0x4. The 32-bit interface requires that
all 4 bytes be written at once, there is not individual byte enables within one 32- bit word.
The transmit data must include the destination address (6 bytes), the source address (6 bytes), the type/length field
(2 bytes), and the data field (0 - 1500 bytes). The preamble, start of frame, and CRC should not be included in the
dual port memory. The destination, source, type/length, and data must be packed together in contiguous memory.
Dual port memory address BASEADDR + 0x07F8 is used to set the global interrupt enable (GIE) bit. Setting the GIE
= ’0’ prevents the IP2INTC_Irpt from going active during an interrupt event. Setting GIE = ’1’ allows the
IP2INTC_Irpt to go active when an interrupt event has occurred.
Dual port memory addresses BASEADDR + 0x07F4 is used to store the length (in bytes) of the transmit data stored
in dual port memory. The higher 8-bits of the length value should be stored in data bits (16 - 23), while the lower 8-
bits should be stored data bits (24 - 31).
The least two significant bits of dual port memory address BASEADDR + 0x07FC are control bits (Program or "P"
and Status or "S") that will be described below. The fourth bit (bit 28 on the data bus) (Transmit Interrupt Enable or
"I") is used to enable transmit complete interrupt events. This event is a pulse and will occur anytime the memory
is ready to accept new data. This includes the completion of programing the MAC address. The transmit complete
interrupt will occur only if GIE and this bit are both set to ’1’.
X-Ref Target - Figure 5
addr offset
0x0
destination
address
source
address
type/
length
addr offset 0x07FC
addr offset 0x07F8
addr offset 0x07F4
addr offset 0x07E4 - 0x07F0
1
data
not
used
6
Note :-
6
2
variable (0 - 1500)
1. MDIO registers are included in the design if the parameter C_INCLUDE_MDIO=1.
variable
Figure 5: Transmit Dual Port Memory
16 4 4 4
DS580_05_041910
Transmit Dual Port Memory Register Description
This section tabulates the transmit dual port memory registers and their reset values. All these register can be access
by single word transaction only. Burst write to these registers will not have any effect on the registers and burst read
from these register will return ‘0’.
Transmit Length Register
The Transmit Length Register is an 32-bit read/write register as shown in Figure 6. This register is used to store the
length (in bytes) of the transmit data stored in dual port memory. The higher 8-bits of the length value should be
DS580 September 21, 2010
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Product Specification