DS580 Datasheet, PDF (5/42 Pages) Xilinx, Inc – Optional MDIO interface for PHY access

LogiCORE IP XPS Ethernet Lite Media Access Controller
Data
The data field may vary from 0 to 1500 bytes in length. This field is transmitted with the least significant bit first.
This field is always provided in the packet data for transmissions and is always retained in the receive packet data.
Pad
The pad field may vary from 0 to 46 bytes in length. This field is used to insure that the frame length is at least 64
bytes in length (the preamble and SFD fields are not considered part of the frame for this calculation) which is
required for successful CSMA/CD operation.
The values in this field are used in the frame check sequence calculation but are not included in the length field
value if it is used. The length of this field and the data field combined must be at least 46 bytes. If the data field con-
tains 0 bytes, the pad field will be 46 bytes. If the data field is 46 bytes or more, the pad field will have 0 bytes.
For transmission, this field will be inserted automatically by the Ethernet Lite MAC if needed to meet the minimum
length requirement. If present during receive packet, this field is always retained in the receive packet data.
FCS
The FCS field is 4 bytes in length. The value of the FCS field is calculated over the source address, destination
address, length/type, data, and pad fields using a 32-bit Cyclic Redundancy Check (CRC) defined as⁽¹⁾:
G(x) = x³² + x²⁶ + x²³ + x²² + x¹⁶ + x¹² + x¹¹ + x¹⁰ + x⁸ + x⁷ + x⁵ + x⁴ + x² + x¹ + x⁰
The CRC bits are placed in the FCS field with the x³¹ term in the left most bit of the first byte and the x⁰ term is the
right most bit of the last byte (i.e., the bits of the CRC are transmitted in the order x³¹, x³⁰,..., x¹, x⁰).
The Ethernet Lite MAC implementation of the CRC algorithm calculates the CRC value a nibble at a time to coin-
cide with the data size exchanged with the external PHY interface for each transmit and receive clock period.
For transmission, this field is always inserted automatically by the Ethernet Lite MAC and is always retained in the
receive packet data.
X-Ref Target - Figure 2
7
Preamble
1
Start of Frame
Delimiter (SFD)
6
Destination
Address
6
2
Source Address Type/Length
0 - 1500
Data
0 - 46
Pad
4
Frame Check
Sequence
64 - 1518 bytes
Figure 2: Ethernet Data Frame
DS80_02_041910
Interframe Gap⁽²⁾ and Deferring
Frames are transmitted over the serial interface with an interframe gap which is specified by the IEEE Std. 802.3 to
be 96 bit times (9.6 uS for 10 MHz and 0.96 uS for 100 MHz). The process for deferring is different for half-duplex
and full-duplex systems and is as follows:
1. Reference IEEE Std. 802.3 para. 3.2.8
2. Interframe Gap and interframe spacing are used interchangeably and are equivalent.
DS580 September 21, 2010
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Product Specification