DS580 Datasheet, PDF (26/42 Pages) Xilinx, Inc – Optional MDIO interface for PHY access

LogiCORE IP XPS Ethernet Lite Media Access Controller
Table 13: XPS Ethernet Lite MAC Design Parameters (Cont’d)
Generic
Feature /
Description
Parameter
Name
Allowable
Values
Default
Value
VHDL
Type
Include Internal Loop C_INCLUDE_INTERNAL_ 1 = Include internal loop
G17
back
LOOPBACK ^[6]
back support
0 = No internal loop back
0
support
integer
Include global buffers C_INCLUDE_GLOBAL_B 1 = Include global buffers
G18
for PHY clocks
UFFERS ^[7]
for PHY clocks
0 = Use normal input
0
buffers for PHY clocks
integer
1. Address range specified by C_BASEADDR and C_HIGHADDR must be at least 0X2000 and must be a power of 2.
C_BASEADDR must be a multiple of the range, where the range is C_HIGHADDR - C_BASEADDR + 1
2. No default value will be specified for values to insure that the actual value is set, i.e if the value is not set, a compiler error will be
generated. The address range must be at least 1FFF
3. For example, C_BASEADDR = 0xE0000000, C_HIGHADDR = 0xE0001FFF
4. The PLB clock frequency must be ≥ 50 MHz for 100 Mbps ethernet operation and greater than or equal to 5 MHz for 10 Mbps
ethernet operation
5. Including MDIO interface allows PHY register access from XPS Ethernet Lite MAC core.
6. Enabling this parameter includes BUFG for PHY clock switching when loop back is enabled.
7. Enabling this parameter includes global buffers for PHY clocks which can be used to minimize the clock skew on the PHY clocks.
Allowable Parameter Combinations
The XPS Ethernet Lite MAC is a synchronous design. Due to the state machine control architecture of receive and
transmit operations, the PLB Clock must be greater than or equal to 50 MHz to allow ethernet operation at 100 Mbps
and greater than or equal to 5 MHz for ethernet operation at 10 Mbps.
The address range specified by C_BASEADDR and C_HIGHADDR must be a power of 2, and C_HIGHADDR range
must be at least 0x2000. For example, if C_BASEADDR = 0xE0000000, C_HIGHADDR must be at least =
0xE0001FFF.
For Spartan-6 family the parameter C_INCLUDE_GLOBAL_BUFFERS must be set to 0 because of the architecture
limitation.
XPS Ethernet Lite MAC Port Dependencies
The dependencies between the XPS Ethernet Lite MAC design parameters and I/O signals are described in
Table 14. In addition, when certain features are parameterized out of the design, the related logic will no longer be
apart of the design. The unused input signals and related output signals are set to a specified value.
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DS580 September 21, 2010
Product Specification