DS580 Datasheet, PDF (15/42 Pages) Xilinx, Inc – Optional MDIO interface for PHY access

LogiCORE IP XPS Ethernet Lite Media Access Controller
Table 5: Receive Control Register Bit Definitions (C_BASEADDR + 0x17FC)
Bit
Name
Access Reset value
Description
0-27 Reserved
N/A
N/A
Reserved
28
Interrupt
Enable
Read/Write
Receive Interrupt Enable bit
‘0’
0 - Disable receive interrupt
1 - Enable receive interrupt
29-30 Reserved
N/A
N/A
Reserved
31
Status
Read/Write
Receive status indicator
0 - Receive ping buffer is empty. Ethernet Lite MAC can accept new
‘0’
available valid packet.
1 - Indicates presence of receive packet ready for software
processing. Once software reads the packet from the receive ping
buffer, software must clears this bit.
Receive Control Register (Pong)
The Receive Control Register for pong buffer is an 32-bit read/write register as shown in Figure 12. This register is
used to inform about the availability of new packet in the pong buffer. The bit definition and accessibility of this reg-
ister is shown in Table 6.
X-Ref Target - Figure 12
Reserved
Status(S)
0
30 31
DS580_12_041910
Figure 12: Receive Control Register
Table 6: Receive Control Register Bit Definitions (C_BASEADDR + 0x1FFC)
Bit
Name
Access Reset value
Description
0-30
Reserved
N/A
N/A
Reserved
Receive status indicator
0 - Receive pong buffer is empty. Ethernet Lite MAC can
31
Status
Read/Write
‘0’
accept new available valid packet.
1 - Indicates presence of receive packet ready for software
processing. Once software reads the packet from the receive
pong buffer, software must clears this bit.
Software Sequence for Receive with Ping Buffer
The proper software sequence for processing a receive is as follows:
• The software monitors the receive Status bit until it is set to ’1’ by the Ethernet Lite MAC, waits for a receive
complete interrupt if enabled
• Once the Status is set to ’1’, or a receive complete interrupt has occurred, the software reads the entire receive
data out of the dual port memory
• The software writes a ’0’ to the receive Status bit enabling the Ethernet Lite MAC to resume receive processing
DS580 September 21, 2010
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Product Specification