DS580 Datasheet, PDF (40/42 Pages) Xilinx, Inc – Optional MDIO interface for PHY access

LogiCORE IP XPS Ethernet Lite Media Access Controller
X-Ref Target - Figure 28
XCL
XCL
MPMC
XPS CDMA XPS CDMA
Device Under
Test (DUT)
MicroBlaze™
Processor
PLBV46
XPS BRAM XPS INTC
XPS GPIO
XPS UART
Lite
MDM
DS580_28_041910
Figure 28: Virtex-6 LXT FPGA System with the XPS Ethernet Lite MAC as the DUT
X-Ref Target - Figure 29
MPMC
XPS CDMA XPS CDMA
Device Under
Test (DUT)
MicroBlaze™
Processor
PLBV46
XPS BRAM XPS INTC
XPS GPIO
XPS UART
Lite
MDM
DS580_29_041910
Figure 29: Spartan-6 LXT FPGA System with the XPS Ethernet Lite MAC as the DUT
The target FPGA was then filled with logic to drive the LUT and BRAM utilization to approximately 70% and the
I/O utilization to approximately 80%. Using the default tool options and the slowest speed grade for the target
FPGA, the resulting target F_MAX numbers are shown in Table 21.
Table 21: XPS Ethernet Lite MAC System Performance
Target FPGA
S3ADSP3400-4
Target F_MAX (MHz)
90
S6LX45T-2
92
V4FX60 -10
100
V5FXT70 -1
120
V6LX130T-1
136
The target F_MAX is influenced by the exact system and is provided for guidance. It is not a guaranteed value across
all systems.
Reference Documents
1. IBM CoreConnect 128-Bit Processor Local Bus: Architecture Specifications version 4.6.
2. IEEE Std. 802.3 Media Independent Interface Specification.
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DS580 September 21, 2010
Product Specification