DS580 Datasheet, PDF (1/42 Pages) Xilinx, Inc – Optional MDIO interface for PHY access

DS580 September 21, 2010
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LogiCORE IP XPS Ethernet Lite
Media Access Controller
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Product Specification
Introduction
The Ethernet Lite MAC (Media Access Controller) is
designed to incorporate the applicable features
described in the IEEE Std. 802.3 Media Independent
Interface (MII) specification, which should be used as
the definitive specification.
The Ethernet Lite MAC supports the IEEE Std. 802.3
Media Independent Interface (MII) to industry stan-
dard Physical Layer (PHY) devices and communicates
to a processor via a Processor Local Bus (PLB) interface.
The design provides a 10 megabits per second (Mbps)
and 100 Mbps (also known as Fast Ethernet) Interface.
The goal is to provide the minimal functions necessary
to provide an Ethernet interface with the least resources
used.
Features
• Connects as 32-bit slave on PLB V4.6 buses of 32,
64 or 128 bits
• Supports single beat and burst transactions
• Memory mapped direct I/O interface to the
transmit and receive data dual port memory
• Media Independent Interface (MII) for connection
to external 10/100 Mbps PHY transceivers
• Independent internal 2K byte Tx and Rx dual port
memory for holding data for one packet
• Optional dual buffer memories, 4K byte ping-
pong, for Tx and Rx
• Receive and Transmit Interrupts
• Optional MDIO interface for PHY access
• Internal loop back support
LogiCORE IP Facts
Core Specifics
Supported Device
Family
Virtex^®-6, Spartan^®-6, Virtex-5/5FX,
Virtex-4/4QV/4Q, Automotive
Spartan-3/3A/3A DSP/3E, Spartan-
3E, Spartan-3, Spartan-3A, Spartan-
3A DSP
Version of core
4.00a
Resources Used
See Table 16,Table 17, Table 18,
Table 19, and Table 20.
Special Features
N/A
Provided with Core
Documentation
Product Specification
Design File
Formats
VHDL
Constraints File
N/A
Verification
N/A
Instantiation
Template
N/A
Reference Designs
/Application Notes
N/A
Additional Items
N/A
Design Tool Requirements
Xilinx
Implementation
Tools
ISE® 12.1
Verification
Mentor Graphics® ModelSim: v6.5c
and above
Simulation
Mentor Graphics ModelSim: v6.5c
and above
Synthesis
XST
Support
Provided by Xilinx, Inc.
© 2006-2010 Xilinx, Inc. XILINX, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, and other designated brands included herein are trademarks of Xilinx in the United
States and other countries
DS580 September 21, 2010
www.xilinx.com
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Product Specification