DS580 Datasheet, PDF (39/42 Pages) Xilinx, Inc – Optional MDIO interface for PHY access

LogiCORE IP XPS Ethernet Lite Media Access Controller
X-Ref Target - Figure 25
PLBV46
PLBV46
MPMC5
XPS CDMA
XPS CDMA
Device Under
Test (DUT)
IPLB1 DPLB1
PowerPC ^®405 ^DPLB0
Processor
IPLB0
PLBV46
XPS BRAM XPS INTC
XPS GPIO
XPS UART
Lite
DS580_25_041910
Figure 25: Virtex-4 FX FPGA System with the XPS Ethernet Lite MAC as the DUT
X-Ref Target - Figure 26
PLBV46
PLBV46
MMiiccrrooBBllaazzee™
Processor
XCL
XCL
MPMC5
XPS CDMA
XPS CDMA
Device Under
Test (DUT
PowerPC^® 440
Processor
PLBV46
MC
PPC440
MC DDR2
MDM
XPS INTC
XPS BRAM
XPS UART
Lite
MDM
DS580_26_041910
Figure 26: Virtex-5 FX FPGA System with the XPS Ethernet Lite MAC as the DUT
X-Ref Target - Figure 27
MPMC5
XPS CDMA
XPS CDMA
Device Under
Test (DUT)
MicroBlaze^™
Processor
PLBV46
XPS BRAM XPS INTC
XPS GPIO
XPS UART
Lite
MDM
DS580_27_041910
Figure 27: Spartan-3ADSP FPGA System with the XPS Ethernet Lite MAC as the DUT
DS580 September 21, 2010
www.xilinx.com
39
Product Specification