DS580 Datasheet, PDF (30/42 Pages) Xilinx, Inc – Optional MDIO interface for PHY access

LogiCORE IP XPS Ethernet Lite Media Access Controller
X-Ref Target - Figure 20
First bit
Serial Bit Stream
LSB D0 D1 D2 D3 D4 D5 D6 D7 MSB
First nibble
Second nibble
LSB D0
D1
D2
MSB D3
DS580_20_041910
Figure 20: Byte/Nibble Transmit and Receive Order
PHY_dv
The PHY drives the Receive Data Valid (PHY_dv) signal to indicate that the PHY is driving recovered and decoded
nibbles on the PHY_rx_data(3:0) bus and that the data on PHY_rx_data(3:0) is synchronous to PHY_rx_clk.
PHY_dv is driven synchronously to PHY_rx_clk. PHY_dv remains asserted continuously from the first recovered
nibble of the frame through the final recovered nibble and is negated prior to the first PHY_rx_clk that follows the
final nibble.
In order for a received frame to be correctly received by the Ethernet Lite MAC, PHY_dv must encompass the
frame, starting no later than the Start-of-Frame Delimiter (SFD) and excluding any End-of-Frame delimiter.
This signal is transferred between the PHY_rx_clk and processor clock domains at the asynchronous RX bus FIFO
interface. The PHY will provide a minimum of 10 nS setup and hold time for this signal in reference to PHY_rx_clk.
Figure 21 shows the behavior of PHY_dv during frame reception.
X-Ref Target - Figure 21
PHY_rx_clk
PHY_dv
PHY_er
PHY_rx_data[3:0] preamble SFD D0 D1 D2 D3
CRC
Figure 21: Receive With No Errors
DS580_21_041910
PHY_rx_data(3:0)
The PHY drives the Receive Data bus PHY_rx_data(3:0) synchronously to PHY_rx_clk. PHY_rx_data(3:0) contains
recovered data for each PHY_rx_clk period in which PHY_dv is asserted. PHY_rx_data(0) is the least significant bit.
The Ethernet Lite MAC must not be affected by PHY_rx_data(3:0) while PHY_dv is de-asserted.
Also, the Ethernet Lite MAC should ignore a special condition that occurs while PHY_dv is de-asserted when the
PHY may provide a False Carrier indication by asserting the PHY_rx_er signal while driving the value 1110 onto
PHY_rx_data(3:0). This bus is transferred between the PHY_rx_clk and processor clock domains at the asynchro-
nous RX bus FIFO interface. The PHY will provide a minimum of 10 nS setup and hold time for this signal in refer-
ence to PHY_rx_clk.
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DS580 September 21, 2010
Product Specification