DS580 Datasheet, PDF (2/42 Pages) Xilinx, Inc – Optional MDIO interface for PHY access

LogiCORE IP XPS Ethernet Lite Media Access Controller
Functional Description
The top level block diagram of the XPS Ethernet Lite MAC is shown in Figure 1.
X-Ref Target - Figure 1
XPS Ethernet Lite MAC
Phy_tx_clk
1
MDIO Master
Interface
PHY _MDC
PHY_MDIO
PLB
Interface
Module
IP2INTC_Irpt
Phy_rx_clk
TX
Buffer
TX
PING
Buffer
2
TX
PONG
Buffer
RX
Buffer
RX
PING
Buffer
3
RX
PONG
Buffer
EMAC
CRC
Generator CRC
TX_Data
SFD
PRE
MUX
TX
FIFO
Transmit
Receive
Receive
Control
Transmit
Control
Loop
Back
Mux
CRC
Checker
RX_Data
RX
FIFO
PHY _tx_ data
TX
Interface
PHY_tx _en
PHY_col
PHY _crs
RX
Interface
PHY _rx_data
PHY _dv
PHY _rx_er
PHY_rst_n
Notes : -
1. MDIO master is included in the design if the parameter C_INCLUDE_MDIO = 1
2. TX PONG Buffer is included in the design if the parameter C_TX_PING_PONG = 1
3. RX PONG Buffer is included in the design if the parameter C_RX_PING_PONG = 1
Figure 1: XPS Ethernet Lite Block Diagram
DS580_01_041910
The XPS Ethernet Lite MAC core consists of following modules:
PLB Interface Module
The PLB Interface Module provides the interface between Ethernet Lite MAC and the PLB. Read and write transac-
tions as the PLB are translated into equivalent IP Interconnect (IPIC) transactions. This module does the necessary
protocol and timing translation between PLB and Ethernet Lite MAC. This module supports single as well as burst
transactions to the Ethernet Lite MAC core.
2
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DS580 September 21, 2010
Product Specification