DS580 Datasheet, PDF (17/42 Pages) Xilinx, Inc – Optional MDIO interface for PHY access

LogiCORE IP XPS Ethernet Lite Media Access Controller
MDIO Address Register (MDIOADDR)
The MDIOADDR is an 32-bit read/write register as shown in Figure 13. This register is used to configure the PHY
device address, PHY register address and type of MDIO transaction. The bit definition and accessibility of this reg-
ister is shown in Table 7.
X-Ref Target - Figure 13
Reserved
OP
PHY Address
Register Address
0
20 21 22
26 27
31
DS580_13_041910
Figure 13: MDIO Address Register
Table 7: MDIO Address Register Bit Definition (C_BASEADDR + 0x07E4)
Bit
Name
Access
Reset
Value
Description
0-20
Reserved
N/A
N/A
Reserved
Operation Access Type
21
OP
Read/Write
‘0’
0 - Write Access
1 - Read Access
22-26
PHYADDR
Read/Write
“00000” PHY device address
27-31
REGADDR
Read/Write
“00000” PHY register address
MDIO Write Data Register (MDIOWR)
The MDIOWR is an 32-bit read/write register as shown in Figure 14. This register contains 16-bit data to be written
in to the PHY register. The bit definition and accessibility of this register is shown in Table 8.
X-Ref Target - Figure 14
Reserved
MDIO Write Data
0
15 16
31
DS580_14_041910
Figure 14: MDIO Write Data Register
Table 8: MDIO Write Data Register Bit Definition (C_BASEADDR + 0x07E8)
Bit
Name
Access
Reset
Value
Description
0-15
Reserved
N/A
N/A
Reserved
16-31
Write Data
Read/Write
0x0000 MDIO write data to be written to PHY register
MDIO Read Data Register (MDIORD)
The MDIORD is an 32-bit read/write register as shown in Figure 15. This register contains 16-bit read data from the
PHY register. The bit definition and accessibility of this register is shown in Table 9.
X-Ref Target - Figure 15
Reserved
MDIO Read Data
0
15 16
31
DS580_15_041910
Figure 15: MDIO Read Data Register
DS580 September 21, 2010
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Product Specification