DS580 Datasheet, PDF (13/42 Pages) Xilinx, Inc – Optional MDIO interface for PHY access

LogiCORE IP XPS Ethernet Lite Media Access Controller
The proper software sequence for initiating a transmit with both a ping and pong buffer is as follows:
• The software stores the transmit data in the dual port memory starting at address offset 0x0
• The software writes the length data in the dual port memory at address offset 0x07F4
• The software writes a ’1’ to the Status bit at address offset 0x07FC (bit 31 on the data bus)
• The software may write to the pong buffer (0x0800 - 0x0FFC) at any time
• The software monitors the Status bit in the ping buffer and waits until it is set to ’0’, or waits for a transmit
complete interrupt, before filling the ping buffer again
• If the transmit interrupt and the global interrupt are both enabled, an interrupt will occur when the Ethernet
Lite MAC clears the Status bit
• The transmit interrupt if enabled will also occur with the completion of writing the MAC address
Setting the Status bit to a ’1’ initiates the Ethernet Lite MAC transmit which will perform the following functions:
• Generate the preamble and start of frame fields
• Read the length and the specified amount of data out of the dual port memory according to the length value
adding padding if required
• Detect any collision and performing any jamming, backoff, and retry if necessary
• Calculates the CRC and appends it to the end of the data
• Clears the status bit at the completion of the transmission
• Clearing the status bit will cause a transmit complete interrupt if enabled
• The hardware will than transmit the pong buffer if it is available, or begin monitoring both ping and pong
buffers until data is available
MAC Address
The 48-bit MAC address defaults at reset to 00-00-5E-00-FA-CE. This value can be changed by performing an
address program operation via the transmit dual port memory.
The proper software sequence for programming a new MAC address is as follows:
• The software loads the new MAC address, in the transmit dual port memory starting at address offset 0x0. The
most significant four bytes are stored at address offset 0x0 and the least significant two bytes are stored at
address offset 0x4. The MAC address may also be programmed from the pong buffer starting at 0x0800
• The software writes a ’1’ to both the Program bit (bit 30 on the data bus) and the Status bit (bit 31 on the data
bus) at address offset 0x07FC. The pong buffer address is 0x0FFC
• The software monitors the Status and Program bits and waits until they are set to ‘0’s before performing any
additional ethernet operations
• A transmit complete interrupt, if enabled, will occur when the Status and Program bits are cleared
Receive Interface
The entire received frame data from destination address to the end of the CRC is stored in the receive dual port
memory area which starts at address BASEADDR + 0x1000. The preamble and start of frame fields are not stored in
dual port memory.
Dual port memory address offset 0x17FC (bit 31 on the data bus) is used as a status to indicated the presence of a
receive packet that is ready for processing by the software.
Dual port memory address offset 0x17FC (bit 28 on the data bus) is the Receive Interrupt enable. This event is a
pulse and will occur anytime the memory has data available. The receive complete interrupt will occur only if GIE
and this bit are both set to ’1’.
DS580 September 21, 2010
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Product Specification