DS580 Datasheet, PDF (19/42 Pages) Xilinx, Inc – Optional MDIO interface for PHY access

LogiCORE IP XPS Ethernet Lite Media Access Controller
• After completing MDIO write transaction, Ethernet Lite MAC will clear the status bit.
• The software monitors the Status bit and waits until it is set to ’0’ by the Ethernet Lite MAC before initiating
new transaction on MDIO lines.
• The proper software sequence for initiating a PHY register Read transaction is as follows:
• The software reads MDIOCTRL register to verify if MDIO master is busy in executing previous request. If the
Status bit is ‘0’, MDIO master can accept new request.
• The software stores the PHY device address and PHY register address and writes ‘1’ in bit 21 in MDIOADDR
register at address offset 0x07E4.
• The software writes ‘1’ in MDIO enable bit in MDIOCTRL register at address offset 0x07F0.
• The software writes a ’1’ to the Status bit at address offset 0x07F0 (bit 31 on the data bus) to start the MDIO
transaction.
• After completing MDIO Read transaction, Ethernet Lite MAC will clear the status bit.
• The software monitors the Status bit and waits until it is set to ’0’ by the Ethernet Lite MAC before initiating
new transaction on MDIO lines.
Internal Loop back Mode
The XPS Ethernet Lite MAC core can be configured in internal loop back mode when the parameter
C_INCLUDE_INTERNAL_LOOPBACK is set to ‘1’ and by setting bit 27 of Transmit Control Register (Ping).
Including the loop back logic uses BUFG for PHY clock switching. In this mode, the Ethernet Lite MAC core route
back data on TX lines on RX line. Loop back mode can be tested only in full duplex mode. In this mode, core does
not accept any data from PHY and PHY_tx_clk and PHY_tx_en are used as PHY_rx_clk and PHY_dv internally as
shown in Figure 17.
DS580 September 21, 2010
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Product Specification