DS580 Datasheet, PDF (20/42 Pages) Xilinx, Inc – Optional MDIO interface for PHY access

LogiCORE IP XPS Ethernet Lite Media Access Controller
X-Ref Target - Figure 17
Processor Bus Interface
Ethernet Lite MAC IP
PLBv46 Slave Interface
Dual Port
Memory
TX
Control
Ethernet Lite
MAC Core
Pong Dual
Port
Memory
Pong Dual
Port
Memory
Dual Port
Memory
RX
Control
TX Bus
FIFO
Transmit
Control
Register
PHY_tx_en
PHY_tx_data
PHY_tx_clk
Loop back
Control
RX Bus
FIFO
Loop Back
Mux
PHY_dv
PHY_rx_data
PHY_rx_clk
PHY_tx_clk
MII Interface
(to external PHY)
PHY_dv
PHY_rx_clk
PHY_rx_data
Figure 17: Internal Loop back Mode
DS580_17_041910
XPS Ethernet Lite Mac Memory Map
The XPS Ethernet Lite MAC memory map is shown in Table 11.
Table 11: XPS Ethernet Lite MAC Memory Map
Address Offset
Parameter Dependency
0x0000
0x0004
0x0008
0x000C
0x0010 - 0x07E0
Tx PING Buffer
C_TX_PING_PONG = '0' or '1'
Memory Location Function
Destination Address Bytes 0 - 3
or
MAC Address Bytes 0 - 3
Destination Address Bytes 4 - 5
Source Address Bytes 0 - 1
or
MAC Address Bytes 4 - 5
Source Address Bytes 2 - 5
Type/Length Field
Data Field Bytes 0 - 1
Remaining Data Field Bytes
20
www.xilinx.com
DS580 September 21, 2010
Product Specification