DS580 Datasheet, PDF (23/42 Pages) Xilinx, Inc – Optional MDIO interface for PHY access

LogiCORE IP XPS Ethernet Lite Media Access Controller
Table 12: XPS Ethernet Lite MAC I/O Signal Description (Cont’d)
Port
Signal Name
Interface I/O
P17 PLB_busLock
P18 PLB_MSize
P19 PLB_lockErr
P20 PLB_wrBurst
P21 PLB_rdBurst
P22 PLB_wrPendReq
P23 PLB_rdPendReq
P24 ^{PLB_wrPendPri[0:1]}
PLB
I
PLB
I
PLB
I
PLB
I
PLB
I
PLB
I
PLB
I
PLB
I
Initial
State
-
-
-
-
-
-
-
-
P25 ^{PLB_rdPendPri[0:1]}
PLB
I
-
P26 PLB_reqPri[0:1]
PLB
I
-
P27 PLB_TAttribute
PLB
I
-
PLB Slave Interface Signals
P28 Sl_addrAck
PLB
O
0
P29 Sl_SSize[0:1]
PLB
O
0
P30 Sl_wait
PLB
O
0
P31 Sl_rearbitrate
PLB
O
0
P32 Sl_wrDAck
PLB
O
0
P33 Sl_wrComp
PLB
O
0
P34 Sl_rdDBus[0:C_SPLB_DWIDTH - 1]
PLB
O
0
P35 Sl_rdDAck
PLB
O
0
P36 Sl_rdComp
PLB
O
0
P37 Sl_MBusy[0:C_SPLB_NUM_MASTERS - 1]
PLB
O
0
P38 Sl_MWrErr[0:C_SPLB_NUM_MASTERS - 1]
PLB
O
0
P39 Sl_MRdErr[0:C_SPLB_NUM_MASTERS - 1]
PLB
O
0
Unused PLB Slave Interface Signals
P40 ^Sl_wrBTerm
PLB
O
0
P41 Sl_rdWdAddr[0:3]
P42 ^Sl_rdBTerm
PLB
O
0
PLB
O
0
P43 Sl_MIRQ[0:C_SPLB_NUM_MASTERS - 1]
PLB
O
0
Ethernet Lite MAC Signals
P44 ^{PHY_rx_data[3:0]}
PHY
I
-
Description
PLB bus lock
PLB data bus width indicator
PLB lock error
PLB burst write transfer
PLB burst read transfer
PLB pending bus write request
PLB pending bus read request
PLB pending write request
priority
PLB pending read request
priority
PLB current request priority
PLB transfer attribute
Slave address acknowledge
Slave data bus size
Slave wait
Slave bus rearbitrate
Slave write data acknowledge
Slave write transfer complete
Slave read data bus
Slave read data acknowledge
Slave read transfer complete
Slave busy
Slave write error
Slave read error
Slave terminate write burst
transfer
Slave read word address
Slave terminate read burst
transfer
Master interrupt request
Ethernet receive data. Input
from Ethernet PHY.
DS580 September 21, 2010
www.xilinx.com
23
Product Specification