DS580 Datasheet, PDF (25/42 Pages) Xilinx, Inc – Optional MDIO interface for PHY access

LogiCORE IP XPS Ethernet Lite Media Access Controller
Table 13: XPS Ethernet Lite MAC Design Parameters (Cont’d)
Generic
Feature /
Description
Parameter
Name
Allowable
Values
Device maximum
G3
address
C_HIGHADDR
Refer to “Allowable
Parameter Combinations”
section
G4
BUS clock period in ps C_SPLB_CLK_PERIOD_ Requirements as stated in
PS
note ^[4]
G5
PLB address bus width C_SPLB_AWIDTH
(in bits)
32
G6
PLB data bus width (in C_SPLB_DWIDTH
bits)
32, 64, 128
G7
Selects point-to-point or C_SPLB_P2P
shared PLB topology
0 = Shared bus topology
PLB Master ID width C_SPLB_MID_WIDTH
log₂
G8
(C_SPLB_NUM_MASTE
RS), with minimum value
of 1
G9
Number of PLB
Masters
C_SPLB_NUM_MASTER 1 - 16
S
G10
Width of IPIF Data Bus C_SPLB_NATIVE_DWIDT 32
H
G11
Width of smallest PLB C_SPLB_SMALLEST_MA 32, 64, 128
Master
STER
G12
Burst Support
C_SPLB_SUPPORT_BUR 0 - 1
STS
Ethernet Lite MAC parameters
Half duplex transmit C_DUPLEX
G13
1 = Only full duplex
operation available
0 = Only half duplex
operation available
Include second transmit C_TX_PING_PONG
G14 buffer
1 = Two transmit buffers
0 = Single memory
transmit buffer
Include second receive C_RX_PING_PONG
G15 buffer
G16
Include MII
Management module
C_INCLUDE_MDIO ^[5]
1 = Two receive buffers
0 = Single memory
receive buffer
1 = Include MDIO module
0 = No MDIO module
Default
Value
None^{[2, 3]}
10000
32
32
0
1
1
32
32
0
1
0
0
1
VHDL
Type
std_logic_
vector
integer
integer
integer
integer
integer
integer
integer
integer
integer
integer
integer
integer
integer
DS580 September 21, 2010
www.xilinx.com
25
Product Specification