DS580 Datasheet, PDF (29/42 Pages) Xilinx, Inc – Optional MDIO interface for PHY access

LogiCORE IP XPS Ethernet Lite Media Access Controller
Processor Bus Clock
The majority of the Ethernet Lite MAC operation functions in the processor bus clock domain. This clock must be
greater than or equal to 50 MHz in order to transmit and receive ethernet data at 100 Mbps and greater than or equal
to 5 MHz in order to transmit and receive ethernet data at 10 Mbps.
PHY Interface Signals
PHY_rst_n
Many PHY devices require that they be held in reset for some period after power becomes valid in order for the
PHY device to be operational following the power-up sequence. The PHY_rst_n signal is an active low reset which
is tied directly to the PLB reset signal (SPLB_Rst). This output signal may be connected to the active low reset input
of a PHY device.
PHY_tx_en
The Ethernet Lite MAC uses the Transmit Enable signal (PHY_tx_en) to indicate to the PHY that it is providing nib-
bles at the MII interface for transmission. It is asserted synchronously to PHY_tx_clk with the first nibble of the pre-
amble and remains asserted while all nibbles have been transmitted. PHY_tx_en is negated prior to the first
PHY_tx_clk following the final nibble of a frame.
This signal is transferred between the PHY_tx_clk and processor clock domains at the asynchronous TX bus FIFO
interface. The clock to output delay of this signal must be 0 to 25 nS. Figure 19 shows PHY_tx_en timing during a
transmission with no collisions.
X-Ref Target - Figure 19
0ns
50ns
100ns
150ns
PHY_tx_clk
PHY_tx_en
PHY_tx_data[3:0] 0
PHY_crs
PHY_col
Preamble
SFD D0 D1
CRC
0
DS580_19_041910
Figure 19: Transmission with no Collision
PHY_tx_data(3:0)
The Ethernet Lite MAC drives the Transmit Data bus PHY_tx_data(3:0) synchronously to PHY_tx_clk.
PHY_tx_data(0) is the least significant bit. The PHY will transmit the value of PHY_tx_data on every clock cycle
that PHY_tx_en is asserted.
This bus is transferred between the PHY_tx_clk and processor clock domains at the asynchronous TX bus FIFO
interface. The clock to output delay of this signal must be 0 to 25 nS. The order of the bits, nibbles, and bytes for
transmit and receive are shown in Figure 20.
DS580 September 21, 2010
www.xilinx.com
29
Product Specification