DS580 Datasheet, PDF (3/42 Pages) Xilinx, Inc – Optional MDIO interface for PHY access

LogiCORE IP XPS Ethernet Lite Media Access Controller
TX Buffer
The TX Buffer module consists of 2K byte dual port memory to hold transmit data for one complete frame and the
transmit interface control registers. It also includes optional 2K byte dual port memory for pong buffer based on the
parameter C_TX_PING_PONG.
RX Buffer
The RX Buffer module consists of 2K byte dual port memory to hold receive data for one complete frame and the
receive interface control register. It also includes optional 2K byte dual port memory for pong buffer based on the
parameter C_RX_PING_PONG.
Transmit
This module consists transmit logic, CRC generator module, transmit data mux, TX FIFO and transmit interface
module. CRC generator module calculates the CRC for the frame need to be transmitted. The transmit control mux
arrange this frame and sends preamble, SFD, frame data, padding and CRC to the transmit FIFO in the required
order. Once the frame is transmitted to PHY, this module generates transmit interrupt and updates the transmit
control register.
Receive
This module consists of RX interface, loop back control mux, RX FIFO, CRC checker and receive control module.
Receive data signals from the PHY are passed through loop back control mux and stored in RX FIFO. If loop back
is enabled, data on TX lines is passed to RX FIFO. The CRC checker module calculates the CRC of the received frame
and if the correct CRC is found, Receive control logic generates the frame receive interrupt.
MDIO Master Interface
MDIO Master Interface module is included in the design if the parameter C_INCLUDE_MDIO is set to ‘1’. This
module provide access to PHY register for PHY management. The MDIO interface is described in "Management
Data Input/Output (MDIO) Master Interface Module".
Ethernet Protocol
Ethernet data is encapsulated in frames as shown in Figure 2. The fields in the frame are transmitted from left to
right. The bits within the frame are transmitted from left to right (from least significant bit to most significant bit
unless specified otherwise).
Preamble
The preamble field is used for synchronization and must contain seven bytes with the pattern “10101010”. The pat-
tern is transmitted from left to right. If a collision is detected during the transmission of the preamble or start of
frame delimiter fields, the transmission of both fields will be completed.
For transmission, this field is always automatically inserted by the Ethernet Lite MAC and should never appear in
the packet data provided to the Ethernet Lite MAC. For reception, this field is always stripped from the packet data.
The Ethernet Lite MAC design does not support the ethernet 8-byte preamble frame type.
DS580 September 21, 2010
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Product Specification