DS580 Datasheet, PDF (28/42 Pages) Xilinx, Inc – Optional MDIO interface for PHY access

LogiCORE IP XPS Ethernet Lite Media Access Controller
Clocks
The Ethernet Lite MAC design has three clock domains that are all asynchronous to each other. The clock domain
diagram for the Ethernet Lite MAC is shown in Figure 18. These clock domains and any special requirements
regarding them are discussed below.
X-Ref Target - Figure 18
Processor Clock Domain
Processor Bus Interface
PLB Interface
Ethernet Lite MAC IP
PLBv46 Slave Single
Dual Port
Memory
Dual Port
Memory
TX
Control
TX Bus
FIFO
Pong Dual
Port
Memory
Pong Dual
Port
Memory
Ethernet Lite MAC Core
RX
Control
RX Bus
FIFO
MII Interface
(to external PHY)
TX Clock Domain RX Clock Domain
Figure 18: Ethernet Lite MAC Clock Domain Diagram
DS580_18_041910
Transmit Clock
The transmit clock [PHY_tx_clk] is generated by the external PHY and must be used by the Ethernet Lite MAC to
provide transmit data [PHY_tx_data (3:0)] and control signals [PHY_tx_en] to the PHY.
The PHY provides one clock cycle for each nibble of data transferred resulting in a 2.5 MHz clock for 10BASE-T
operation and 25 MHz for 100BASE-T operation at +/- 100 ppm with a duty cycle of between 35% and 65% inclu-
sive. The PHY derives this clock from an external oscillator or crystal.
Receive Clock
The receive clock [PHY_rx_clk] is also generated by the external PHY but is derived from the incoming ethernet
traffic. Like the transmit clock, the PHY provides one clock cycle for each nibble of data transferred resulting in a 2.5
MHz clock for 10BASE-T operation and 25 MHz for 100BASE-T operation with a duty cycle of between 35% and
65% inclusive while incoming data is valid [PHY_dv is ’1’].
The minimum high and low times of the receive clock are at least 35% of the nominal period under all conditions.
The receive clock is used by the Ethernet Lite MAC to sample the receive data [PHY_rx_data(3:0)] and control sig-
nals [PHY_dv and PHY_rx_er] from the PHY.
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DS580 September 21, 2010
Product Specification