DS580 Datasheet, PDF (18/42 Pages) Xilinx, Inc – Optional MDIO interface for PHY access

LogiCORE IP XPS Ethernet Lite Media Access Controller
Table 9: MDIO Read Data Register Bit Definition (C_BASEADDR + 0x07EC)
Bit
Name
Access
Reset
Value
Description
0- 15
Reserved
N/A
N/A
Reserved
16-31
Read Data
Read
0x0000 MDIO read data from the PHY register
MDIO Control Register (MDIOCTRL)
The MDIOCTRL is an 32-bit read/write register as shown in Figure 16. This register contains status and control
information of the MDIO interface. The MDIO Enable (bit-28) of this register is used to enable the MDIO interface.
The bit definition and accessibility of this register is shown in Table 10.
X-Ref Target - Figure 16
Reserved
MDIO
Enable(E) ^Status(S)
0
27 28 ^{29 30} 31
DS580_16_060809
Figure 16: MDIO Control Register
Table 10: MDIO Control Register Bit Definition (C_BASEADDR + 0x07F0)
Bit
Name
Access
Reset
Value
Description
0-27
Reserved
N/A
N/A
Reserved
28
MDIO Enable
Read/Write
MDIO enable bit
‘0’
0 - Disable MDIO interface
1 - Enable MDIO interface
29-30
Reserved
N/A
N/A
Reserved
MDIO status bit
0 - MDIO transfer is complete and core is ready to
31
Status
Read/Write
‘0’
accept new MDIO request
1 - MDIO transfer is in progress. Setting this bit will
initiate MDIO transaction. Once MDIO transaction is
complete, Ethernet Lite MAC core clears this bit
MDIO Transactions
The Ethernet Lite MAC requires that the PHY device address and PHY register address to be stored in MDIO
Address Register at address offset 0x07E4 before the software sets the status bit in MDIO Control Register at offset
0x07F0.
The proper software sequence for initiating a PHY register write transaction is as follows:
• The software reads MDIOCTRL register to verify if MDIO master is busy in executing previous request. If the
Status bit is ‘0’, MDIO master can accept new request.
• The software stores the PHY device address and PHY register address and writes ‘0’ in bit 21 in MDIOADDR
register at address offset 0x07E4.
• The software stores the PHY register write data in the MDIOWR register at address offset 0x07E8.
• The software writes ‘1’ in MDIO enable bit in MDIOCTRL register at address offset 0x07F0.
• The software writes a ’1’ to the Status bit at address offset 0x07F0 (bit 31 on the data bus) to start the MDIO
transaction.
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DS580 September 21, 2010
Product Specification