DS580 Datasheet, PDF (8/42 Pages) Xilinx, Inc – Optional MDIO interface for PHY access

LogiCORE IP XPS Ethernet Lite Media Access Controller
Receive Flow
The flow chart in Figure 4 shows the high level flow followed for packet reception.
X-Ref Target - Figure 4
Start
Receive
F _{PHY_dv}
=’1’?
T
Start
Receiving
F Done
Receiving?
T
F _Recognize
Address?
T
Valid
FCS?
T
Done;
Receive OK
F
Done;
FCS Error
DS580_04_041910
Figure 4: Receive Flow
Processor Interface
Single memory buffer Interface, C_TX_PING_PONG = C_RX_PING_PONG = 0
The Ethernet Lite MAC has a very simple interface to the processor. The interface is implemented with a 32-bit wide
data interface to a 4K byte block of dual port memory. The registers are implemented in the dual port memory.
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DS580 September 21, 2010
Product Specification