DS580 Datasheet, PDF (32/42 Pages) Xilinx, Inc – Optional MDIO interface for PHY access

LogiCORE IP XPS Ethernet Lite Media Access Controller
PHY_col
The PHY drives the Collision detected signal (PHY_col) active to indicate the detection of a collision on the bus. The
PHY drives PHY_crs asserted while the collision condition persists. The PHY also drives PHY_col asserted when
operating at 10 Mbps for signal_quality_error (SQE) testing.
PHY_col is not synchronous to either the PHY_tx_clk or the PHY_rx_clk. The PHY_col signal is not used in full
duplex mode. The PHY_col signal is used by both the Ethernet Lite MAC transmit and receive circuitry and is dou-
ble synchronized to the processor clock as it enters the Ethernet Lite MAC. Figure 23 shows the behavior of
PHY_col during frame transmission with a collision.
X-Ref Target - Figure 23
PHY_tx_clk
PHY_tx_en
PHY_tx_data[3:0] 0
PHY_crs
PHY_col
Preamble
JAM
0
DS580_23_041910
Figure 23: Transmission With Collision
Receive Address Validation
Destination addresses are classified as either unicast (a single station address indicated by the I/G bit = ’0’), mul-
ticast (a group of stations indicated by the I/G bit = ’1’), and the multicast subgroup broadcast (all stations on the
network). The Ethernet Lite MAC accepts messages addressed to its unicast address and the broadcast address.
Design Constraints
The Ethernet Lite MAC core is designed to not use global buffers for the Tx and Rx clocks in default condition.
Hence, Ethernet Lite MAC core requires design constraints as shown in Figure 24 to guarantee performance. Please
refer constraints guide for additional constraints, if required. If the global clock buffers are used for TX/RX clocks,
then MAXSKEW constraints are not required. These constraints should be placed in a .UCF file for the top level of
the design. The global clock buffers for TX/RX clocks can be included in the design by setting
C_INCLUDE_GLOBAL_BUFFERS parameter. The following example of the constraint is for 25 Mhz PHY clock and
text is based on the port names of the Ethernet Lite MAC core. If these ports are mapped to FPGA pin names that
are different, the FPGA pin names should be substituted for the port names.
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DS580 September 21, 2010
Product Specification