DS580 Datasheet, PDF (12/42 Pages) Xilinx, Inc – Optional MDIO interface for PHY access

LogiCORE IP XPS Ethernet Lite Media Access Controller
Table 4: Transmit Control Register Bit Definitions (C_BASEADDR + 0x0FFC)
Bit
Name
Access
Reset value
Description
0-29
Reserved
N/A
N/A
Reserved
30
Program
Read/Write
Ethernet Lite MAC address program bit.
‘0’
Setting this bit and Status bit will configure the new MAC
address for the core as described in MAC Address.
31
Status
Read/Write
Transmit pong buffer status indicator
0 - Transmit pong buffer is ready to accept new frame
‘0’
1 - Frame transfer is in progress. Setting this bit will
initiate transmit transaction. Once transmit is complete,
Ethernet Lite MAC core clears this bit.
Software Sequence for Transmit with Ping Buffer
The Ethernet Lite MAC requires that the length of the transmit data be stored in address offset 0x07F4 before the
software sets the status bit at offset 0x07FC.
• The proper software sequence for initiating a transmit is as follows:
• The software stores the transmit data in the dual port memory starting at address offset 0x0
• The software writes the length data in the dual port memory at address offset 0x07F4
• The software writes a ’1’ to the Status bit at address offset 0x07FC (bit 31 on the data bus)
• The software monitors the Status bit and waits until it is set to ’0’ by the Ethernet Lite MAC before initiating
another transmit
• If the transmit interrupt and the global interrupt are both enabled, an interrupt will occur when the Ethernet
Lite MAC clears the Status bit
• The transmit interrupt if enabled will also occur with the completion on writing the MAC address
Setting the Status bit to a ’1’ initiates the Ethernet Lite MAC transmit which will perform the following functions:
• Generate the preamble and start of frame fields
• Read the length and the specified amount of data out of the dual port memory according to the length value
adding padding if required
• Detect any collision and performing any jamming, backoff, and retry if necessary
• Calculates the CRC and appends it to the end of the data
• Clears the status bit at the completion of the transmission
• Clearing the status bit will cause a transmit complete interrupt if enabled
Transmit Ping-Pong
If C_TX_PING_PONG is set to 1 then two memory buffers exist for the transmit data. The original (ping transmit
buffer) remains at the same memory address and controls the global interrupt enable. The second (pong buffer) is
mapped at BASEADDR + 0x0800 through 0x0FFC. The length and status must be used in the pong buffer the same
as in the ping buffer. The I bit and GIE bit are not used from the pong buffer (i.e., the I bit and GIE bit of the ping
buffer alone control the I bit and GIE bit settings for both buffers). The MAC address may be set from the pong
buffer. The transmitter will always empty the ping buffer first after a reset. Then if data is ready to be transmitted
from the pong buffer that will occur. However, if the pong buffer is not ready to transmit data the Ethernet Lite
MAC will begin to monitor both the ping and pong buffer and transmit which ever buffer is ready first.
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DS580 September 21, 2010
Product Specification