DS580 Datasheet, PDF (24/42 Pages) Xilinx, Inc – Optional MDIO interface for PHY access

LogiCORE IP XPS Ethernet Lite Media Access Controller
Table 12: XPS Ethernet Lite MAC I/O Signal Description (Cont’d)
Port
Signal Name
Interface I/O
P45 ^{PHY_tx_data[3:0]}
PHY
O
P46 ^PHY_dv
PHY
I
P47 ^PHY_rx_er
PHY
I
P48 ^PHY_tx_en
PHY
O
P49 PHY_tx_clk
P50 PHY_rx_clk
P51 ^PHY_crs
PHY
I
PHY
I
PHY
I
P52 ^PHY_col
PHY
I
P53 ^PHY_rst_n
PHY
O
P54 ^PHY_MDC
PHY
O
P55 ^PHY_MDIO_I
PHY
I
P56 ^PHY_MDIO_O
PHY
O
P57 ^PHY_MDIO_T
PHY
O
Initial
State
0
-
-
0
-
-
-
-
1
0
-
0
0
Description
Ethernet transmit data. Output
to Ethernet PHY.
Ethernet receive data valid.
Input from Ethernet PHY.
Ethernet receive error. Input
from Ethernet PHY.
Ethernet transmit enable.
Output to Ethernet PHY.
Ethernet transmit clock
Ethernet receive clock
Ethernet carrier sense input
from Ethernet PHY
Ethernet collision input from
Ethernet PHY
Ethernet PHY reset output to
Ethernet PHY
Ethernet to PHY MII
Management clock
PHY MDIO data input from 3-
state buffer
PHY MDIO data output to 3-
state buffer
PHY MDIO data output enable
to 3-state buffer
XPS Ethernet Lite MAC Design Parameters
To obtain an XPS Ethernet Lite MAC that is uniquely tailored to the user system requirements, certain features can
be parameterized in the XPS Ethernet Lite MAC design. This allows a design that utilizes only the resources
required by the system and runs at the best possible performance. Table 13 lists the features that can be parameter-
ized in the Xilinx XPS Ethernet Lite MAC design.
Table 13: XPS Ethernet Lite MAC Design Parameters
Generic
Feature /
Description
Parameter
Name
Allowable
Values
Default
Value
VHDL
Type
System parameters
Device family
G1
C_FAMILY
aspartan3, spartan3,
spartan3a, spartan3e,
aspartan3e, aspartan3a,
aspartan3adsp, spartan6,
virtex4, qrvirtex4,
qvirtex4, virtex5, virtex6
virtex5
string
PLB parameters
G2
Device base address C_BASEADDR
Valid word aligned
address range^[1]
None^{[2, 3]}
std_logic_
vector
24
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DS580 September 21, 2010
Product Specification