DS580 Datasheet, PDF (27/42 Pages) Xilinx, Inc – Optional MDIO interface for PHY access

LogiCORE IP XPS Ethernet Lite Media Access Controller
Table 14: XPS Ethernet Lite MAC Parameter - Port Dependencies
Generic
or Port
Name
Affects Depends
Relationship Description
Design Parameters
G5
C_SPLB_AWIDTH
P4
-
Width of the PLB Address Bus
G6
C_SPLB_DWIDTH
P8, P11, P34
-
Width of the PLB Data Bus and PLB Slave Data Bus
G8
C_SPLB_MID_
WIDTH
P6
-
Width of the PLB Address Bus
G9
C_SPLB_NUM_
MASTERS
P37, P38,
P39, P43
-
Width of number of masters
G16
C_INCLUDE_MDIO
P54, P55
PHY_MDC and PHY_MDIO are included in the core only
if C_INCLUDE_MDIO = 1
I/O Signals
P4
PLB_ABus[0:C_
SPLB_AWIDTH - 1]
-
G5
Width of the PLB Address Bus varies according to
C_SPLB_AWIDTH
PLB_masterID[0:C_S
P6
PLB_MID_
-
WIDTH - 1]
Width of the PLB_masterID varies according to
G8
C_SPLB_MID_WIDTH
P8
PLB_BE[0:(C_SPLB_
DWIDTH/8) - 1]
-
G6
Width of the PLB Byte Enable varies according to
C_SPLB_DWIDTH
P11
PLB_wrDBus[0:C_SP
LB_DWIDTH - 1]
-
G6
Width of the PLB WriteData Bus varies according to
C_SPLB_DWIDTH
P34
Sl_rdBus[0:C_
SPLB_DWIDTH - 1]
-
G6
Width of the Slave Read Data Bus varies according to
C_SPLB_DWIDTH
Sl_MBusy[0:C_
P37 SPLB_NUM_MASTER
-
S - 1]
Width of the Sl_MBusy varies according to
G9
C_SPLB_NUM_MASTERS
Sl_MWrErr[0:C_
P38 SPLB_NUM_MASTER
-
S - 1]
Width of the Sl_MWrErr varies according to
G9
C_SPLB_NUM_MASTERS
Sl_MRdErr[0:C_
P39 SPLB_NUM_MASTER
-
S - 1]
Width of the Sl_MRdErr varies according to
G9
C_SPLB_NUM_MASTERS
Sl_MIRQ[0:C_
P43 SPLB_NUM_MASTER
-
S - 1]
Width of the Sl_MIRQ varies according to
G9
C_SPLB_NUM_MASTERS
P54
PHY_MDC
-
G16
This port is included in the core only if
C_INCLUDE_MDIO = 1
P55
PHY_MDIO_I
-
G16
This port is included in the core only if
C_INCLUDE_MDIO = 1
P56
PHY_MDIO_O
-
G16
This port is included in the core only if
C_INCLUDE_MDIO = 1
P57
PHY_MDIO_T
-
G16
This port is included in the core only if
C_INCLUDE_MDIO = 1
DS580 September 21, 2010
www.xilinx.com
27
Product Specification