DS580 Datasheet, PDF (10/42 Pages) Xilinx, Inc – Optional MDIO interface for PHY access

LogiCORE IP XPS Ethernet Lite Media Access Controller
stored in data bits (16 - 23), while the lower 8-bits should be stored data bits (24 - 31). The bit definition and acces-
sibility of this register for Ping and Pong buffer interface is shown in Table 1.
X-Ref Target - Figure 6
Reserved
Frame Length
MSB
Frame Length
LSB
0
15 16
23 24
31
DS580_06_041910
Figure 6: Transmit Length Register
Table 1: Transmit Length Register Bit Definitions (C_BASEADDR + 0x07F4),(C_BASEADDR + 0x0FF4)
Bit
Name
Access
Reset value
Description
0-15
Reserved
N/A
N/A
Reserved
16-23
MSB
Read/Write
“0x00”
The higher 8-bits of the frame length
24-31
LSB
Read/Write
“0x00”
The lower 8-bits of the frame length
Global Interrupt Enable Register (GIE)
The Global Interrupt Enable Register is an 32-bit read/write register as shown in Figure 7. The GIE register is used
to enable transmit complete interrupt events. This event is a pulse and will occur anytime the memory is ready to
accept new data. This includes the completion of programing the MAC address. The transmit complete interrupt
will occur only if GIE and transmit/receive interrupt enable bit are both set to ’1’. The bit definition and accessibility
of this register is shown in Table 2.
X-Ref Target - Figure 7
Global Interrupt
Enable (GIE)
Reserved
01
Figure 7: Global Interrupt Enable
31
DS580_07_041910
Table 2: Global Interrupt Enable Register Bit Definitions (C_BASEADDR + 0x07F8)
Bit
Name
Access
Reset value
Description
0
GIE
Read/Write
‘0’
Global Interrupt Enable bit
1-31
Reserved
N/A
N/A
Reserved
10
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DS580 September 21, 2010
Product Specification