DS580 Datasheet, PDF (16/42 Pages) Xilinx, Inc – Optional MDIO interface for PHY access

LogiCORE IP XPS Ethernet Lite Media Access Controller
Receive Ping-Pong
If C_RX_PING_PONG is set to ’1’ then two memory buffers exist for the receive data. The original (ping receive
buffer) remains at the same memory location. The second (pong receiver buffer) is mapped at BASEADDR + 0x1800
through 0x1FFC. Data is stored the same in the pong buffer as it is in the ping buffer.
The proper software sequence for processing a receive packet(s) with C_RX_PING_PONG = 1 is as follows:
• The software monitors the ping receive Status bit until it is set to ’1’ by the Ethernet Lite MAC, or waits for a
receive complete interrupt if enabled
• Once the ping Status is set to ’1’, or a receive complete interrupt has occurred, the software reads the entire
receive data out of the ping dual port memory
• The Ethernet Lite MAC will receive the next packet and store it in the pong receive buffer
• The software writes a ’0’ to the ping receive Status bit enabling the Ethernet Lite MAC to receive another
packet in the ping receive buffer
• The software monitors the pong receive Status bit until it is set to ’1’ by the Ethernet Lite MAC, or waits for a
receive complete interrupt if enabled
• Once the pong Status is set to ’1’, or a receive complete interrupt has occurred, the software reads the entire
receive data out of the ping dual port memory
• The hardware will always write the first received packet after a reset to the ping buffer, the second received
packet will be written to the pong buffer and the third received packet will be written to the ping buffer
Management Data Input/Output (MDIO) Master Interface Module
The Management Data Input/Output Master Interface module is included in the design if the parameter
C_INCLUDE_MDIO = 1. Including this logic allows Ethernet Lite MAC core to access PHY configuration registers.
The MDIO Master Interface module is designed to incorporate the features described in IEEE 802.3 Media Indepen-
dent Interface (MII) specification.
The MDIO module generates management data clock to the PHY(PHY_MDC) with minimum period of 400 ns.
PHY_MDC is sourced to PHY as timing reference for transfer of information on the PHY_MDIO (Management Data
Input/Output) data signal.
PHY_MDIO is a bi-directional signal between the PHY and MDIO module. It is used to transfer control and status
information between the PHY and the MDIO module. The control information is driven by the MDIO module syn-
chronously with respect to PHY_MDC and is sampled synchronously by the PHY. The status information is driven
by the PHY synchronously with respect to PHY_MDC and is sampled synchronously by the MDIO module.
PHY_MDIO is driven through three-state circuit that enable either the MDIO module or the PHY to drive the cir-
cuit.
The MDIO interface uses standard method to access PHY management registers. The MDIO module supports up to
32 PHY devices. To access each PHY devices, the PHY device address must be written into the MIDO Address
(MDIOADDR) register followed by PHY register address as shown in Figure 13. This module supports up 32 PHY
management registers access. The write transaction data for the PHY must be written into MDIO Write Data
(MDIOWR) register and the status data from the PHY register can be read from MDIO Read Data (MDIORD) reg-
ister. The MDIO Control (MDIOCTRL) register is used to initiate to management transaction on the MDIO lines.
MDIO Register Descriptions
This section tabulates the MDIO registers and their reset values. All these register can be access by single word
transaction only. Burst write to these registers will not have any effect on the registers and burst read from these reg-
ister will return ‘0’.
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DS580 September 21, 2010
Product Specification