DS580 Datasheet, PDF (33/42 Pages) Xilinx, Inc – Optional MDIO interface for PHY access

LogiCORE IP XPS Ethernet Lite Media Access Controller
X-Ref Target - Figure 24
Common Constraints for all FPGA devices
NET "phy_rx_clk" PERIOD = 40 ns HIGH 14 ns;
NET "phy_tx_clk" PERIOD = 40 ns HIGH 14 ns;
OFFSET = OUT 10 ns AFTER "phy_tx_clk" ;
OFFSET = IN 6 ns BEFORE "phy_rx_clk" ;
NET "SPLB_Rst" TIG;
NET "phy_rx_data<3>" IOBDELAY = NONE;
NET "phy_rx_data<2>" IOBDELAY = NONE;
NET "phy_rx_data<1>" IOBDELAY = NONE;
NET "phy_rx_data<0>" IOBDELAY = NONE;
NET "phy_dv" IOBDELAY = NONE;
NET "phy_rx_er" IOBDELAY = NONE;
NET "phy_crs" IOBDELAY = NONE;
NET "phy_col" IOBDELAY = NONE;
Constraints for Spartan-3 FPGA devices
NET "phy_tx_clk" USELOWSKEWLINES;
NET "phy_rx_clk" USELOWSKEWLINES;
NET "phy_tx_clk" MAXSKEW = 5.0 ns;
NET "phy_rx_clk" MAXSKEW = 5.0 ns;
Constraints for Virtex-4, Virtex-5, Virtex6 and
Spartan6 FPGA devices
NET "phy_tx_clk" MAXSKEW = 6.0 ns;
NET "phy_rx_clk" MAXSKEW = 6.0 ns;
Figure 24: Design constraints
DS580_24_041910
Design Implementation
Target Technology
The intended target technology is an FPGA listed in the Supported Device Family field in the LogiCORE Fact Table.
DS580 September 21, 2010
www.xilinx.com
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Product Specification