DS580 Datasheet, PDF (34/42 Pages) Xilinx, Inc – Optional MDIO interface for PHY access

LogiCORE IP XPS Ethernet Lite Media Access Controller
Device Utilization and Performance Benchmarks
Core Performance
To analyze the XPS Ethernet Lite Controller timing within the FPGA, a design was generated that enclosed the Core
in a wrapper. For sizing estimates, a simple wrapper that connected all I/O to the ports of the wrapper was utilized.
For F_MAX, the wrapper was modified to incorporate input and output registers on all input and output ports respec-
tively. The XPS Ethernet Lite MAC resource utilization for various parameter combinations measured with Virtex-
4 as the target device are detailed in Table 16.
Table 16: Ethernet Lite MAC Performance and Resource Utilization for the Virtex-4 FPGA
(Device: xc4vlx40-ff1148-10)
Parameter Values
Device Resources
Performance
Slices
Slice
Flip-Flops
LUTs
Block
RAMS
F_Max
(MHz)
0
0
0
0
0
0
750
808
943
2
125
1
0
0
0
0
0
557
746
809
2
125
1
1
1
0
0
0
721
771
906
4
125
1
1
1
0
1
0
634
816
960
4
125
1
0
0
0
1
0
735
791
862
2
125
1
1
1
1
0
0
870
869
1,063
4
125
1
1
1
1
1
0
903
914
1,116
4
125
1
0
0
1
0
0
814
843
935
2
125
1
0
0
1
1
1
637
888
987
2
125
34
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DS580 September 21, 2010
Product Specification