DS580 Datasheet, PDF (22/42 Pages) Xilinx, Inc – Optional MDIO interface for PHY access

LogiCORE IP XPS Ethernet Lite Media Access Controller
Table 11: XPS Ethernet Lite MAC Memory Map (Cont’d)
Address Offset
Parameter Dependency
Memory Location Function
0x1800
Destination Address Bytes 0 - 3
0x1804
Destination Address Bytes 4 - 5
Source Address Bytes 0 - 1
0x1808
0x180C
Rx PONG Buffer
C_RX_PING_PONG = '1' else
unused
Source Address Bytes 2 - 5
Type/Length Field
Data Field Bytes 0 - 1
0x1810 - 0x1FE0
Remaining Data and CRC Field Bytes
0x1FE4 - 0x1FF8
Reserved
0x1FFC
Control
1. MDIO registers are included in the memory map only if C_INCLUDE_MDIO = 1. If MDIO interface is not enabled, this register
space will be treated as reserved.
XPS Ethernet Lite I/O Signals
The XPS Ethernet Lite MAC I/O signals are listed and described in Table 12.
Table 12: XPS Ethernet Lite MAC I/O Signal Description
Port
Signal Name
Interface I/O
Initial
State
System Signals
P1 SPLB_Clk
P2 SPLB_Rst
P3 IP2INTC_Irpt
System
I
-
System
I
-
System
O
0
PLB Interface Signals
P4 PLB_ABus[0:C_SPLB_AWIDTH - 1]
PLB
I
-
P5 PLB_PAValid
PLB
I
-
P6 PLB_masterID[0:C_SPLB_MID_WIDTH - 1]
PLB
I
-
P7 PLB_RNW
PLB
I
-
P8 PLB_BE[0:(C_SPLB_DWIDTH/8) - 1]
PLB
I
-
P9 PLB_size[0:3]
P10 PLB_type[0:2]
P11 PLB_wrDBus[0:C_SPLB_DWIDTH - 1]
PLB
I
-
PLB
I
-
PLB
I
-
Unused PLB Interface Signals
P12 PLB_UABus[0:C_SPLB_AWIDTH - 1]
P13 PLB_SAValid
P14 ^PLB_rdPrim
PLB
I
-
PLB
I
-
PLB
I
-
P15 ^PLB_wrPrim
PLB
I
-
P16 PLB_abort
PLB
I
-
Description
PLB clock
PLB reset, active high
System Interrupt
PLB address bus
PLB primary address valid
PLB current master identifier
PLB read not write
PLB byte enables
PLB size of requested transfer
PLB transfer type
PLB write data bus
PLB upper Address bits
PLB secondary address valid
PLB secondary to primary read
request indicator
PLB secondary to primary write
request indicator
PLB abort bus request
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DS580 September 21, 2010
Product Specification